ci: shippable: enable parallel build

Try to speed up the Shippable CI by re-introducing parallel builds, which
were removed by commit c330283b4a00 ("ci: .shippable.yml: disable parallel
build") due

ci: shippable: enable parallel build

Try to speed up the Shippable CI by re-introducing parallel builds, which
were removed by commit c330283b4a00 ("ci: .shippable.yml: disable parallel
build") due to random build errors. Although the root cause was never
identified, there are reasons to believe that the issue may not be
reproducible anymore:
- The container environment has likely seen updates
- Commit 836334a163f9 ("ci: shippable: set build directory identically for
all platforms") has modified the output paths, so a race condition on
directory creation seems quite unlikely to happen.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: crypto: cleanup and fix CE accelerated AES CTR

There is a problem with how the counter is incremented in our Aarch32
implementation of ce_aes_ctr_encrypt(). When 3 or more 16-byte blocks of
da

core: crypto: cleanup and fix CE accelerated AES CTR

There is a problem with how the counter is incremented in our Aarch32
implementation of ce_aes_ctr_encrypt(). When 3 or more 16-byte blocks of
data are processed, the counter is incremented one time too many and
invalid data is produced as a result [1].

More generally, the way the counter is handled is quite convoluted. It is
incremented:
- In the generic LibTomCrypt code in ctr_encrypt_sub(),
- In the Crypto Extension glue layer in aes_ctr_encrypt_nblocks(),
- In the CE accelerated assembly code in ce_aes_ctr_encrypt().
We can easily get rid of the second one. We can also avoid always calling
the non-accelerated function on the first block of data.

This commit simplifies the C code to reflect the following rules:
- The core encryption functions (accelerated or not) should use the
counter value as is to process the first block of data,
- They should increment it for each block that is processed and return it
as an output parameter

The AArch32 and AArch64 CE assembler implementations are updated to the
latest available in the upstream Linux kernel (v4.17-rc7), thus
incorporating further improvements/simplifications by Ard Biesheuvel.
These functions handle the counter as described above so they fit our use
case perfectly.

Fixes: [1] https://github.com/OP-TEE/optee_os/issues/2305
CC: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960, 32/64, CE/no CE)
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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tee_ta_manager: remove unused function tee_ta_get_client_id()

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depend

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: shippable: set build directory identically for all platforms

Further improve the ccache hit rate by setting the build directory
to be the same for all platforms. Prior to this, only the build fo

ci: shippable: set build directory identically for all platforms

Further improve the ccache hit rate by setting the build directory
to be the same for all platforms. Prior to this, only the build for
the same platform could share cached files, because the file path is
part of the hash.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: shippable: enable ccache's 'unify' option

There is currently no caching possible between the various _make lines in
.shippable.yml, because they select different configuration flags. Since
all t

ci: shippable: enable ccache's 'unify' option

There is currently no caching possible between the various _make lines in
.shippable.yml, because they select different configuration flags. Since
all the files include $(out-dir)/include/generated/conf.h automatically,
the preprocessor output is therefore different simply due to the fact that
conf.h is different from one line to the other.

This is quite unfortunate, because most source files depend on a handful
of configuration flags only and therefore activating unrelated flags
should not cause a cache miss.

Addressing this problem is exactly the purpose of the 'unify' option of
ccache [1]. Activate it by setting CCACHE_UNIFY=true and CFG_DEBUG_INFO=n
before building. The lines that set DEBUG=0 or DEBUG=1 are adjusted to
produce the same result as before.

Link: [1] https://github.com/ccache/ccache/blob/v3.4.2/doc/MANUAL.adoc#configuration-settings
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (defau

core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (default y)
which selects the C compiler flag -g3 and assembler flag -g.

DEBUG=1 is kept for compatibility.

Being able to compile without -g is useful to get much better performance
from ccache thanks to its 'unify' option [1].

Link: https://github.com/ccache/ccache/blob/v3.4.2/doc/MANUAL.adoc#configuration-settings
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000

plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START be100000 be100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START bfe00000 bfe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE be000000 be000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 0

plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START fe100000 fe100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START ffe00000 ffe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE fe000000 fe000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6UL and MX6ULL

PLATFORM=imx-mx6ulevk

Name Before After
TEE_RAM_START 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000

plat-imx: generic RAM layout for MX6UL and MX6ULL

PLATFORM=imx-mx6ulevk

Name Before After
TEE_RAM_START 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 9e100000 9e100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START 9fe00000 9fe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE 9e000000 9e000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6Q, MX6D, MX6DL, MX6S

The 'after' values are computed with the fix to TA_RAM_SIZE.

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=n

Name Before

plat-imx: generic RAM layout for MX6Q, MX6D, MX6DL, MX6S

The 'after' values are computed with the fix to TA_RAM_SIZE.

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=n

Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=y

Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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TA dev kit: shared library: strip directory part

The symbolic link and its target are in the same directory, so we need
to make sure that there is no relative path before the target filename.
The pr

TA dev kit: shared library: strip directory part

The symbolic link and its target are in the same directory, so we need
to make sure that there is no relative path before the target filename.
The proper Make variable to use is therefore not $< but $(<F).

Fixes: 01b8b5ce011d ("TA dev kit: when building a shared library, create symlink with UUID")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: prevent user_ta resource to be unpaged

Function is_user_ta_ctx() is used by unpaged code. Prior this change,
the whole user_ta_ops structure fell into unpaged sections. This change
decreases t

core: prevent user_ta resource to be unpaged

Function is_user_ta_ctx() is used by unpaged code. Prior this change,
the whole user_ta_ops structure fell into unpaged sections. This change
decreases the unpaged size by few tenths of kBytes.

Below are extracts from mem_usage.py output on qemu_armv8 with
CFG_WITH_PAGER=y and CFG_TEE_CORE_DEBUG=n. Check the size of sections
.text and .rodata.

- Before the change:
RAM Usage 0E100000 - 0E166000 size 00066000 408 KiB 102 pages
.text 0E100000 - 0E1151E8 size 000151E8 84 KiB
.rodata 0E1151E8 - 0E117BD8 size 000029F0 10 KiB
*hole* 0E117BD8 - 0E118000 size 00000428 1 KiB
.data 0E118000 - 0E11A280 size 00002280 8 KiB
.bss 0E11A280 - 0E11CBD8 size 00002958 10 KiB
.heap1 0E11CBD8 - 0E120000 size 00003428 13 KiB
.nozi 0E120000 - 0E12D300 size 0000D300 52 KiB
.heap2 0E12D300 - 0E13A000 size 0000CD00 51 KiB
.text_init 0E13A000 - 0E13EEE0 size 00004EE0 19 KiB
.rodata_init 0E13EEE0 - 0E13FD10 size 00000E30 3 KiB
.rodata_pageable 0E13FD10 - 0E144080 size 00004370 16 KiB
.text_pageable 0E144080 - 0E166000 size 00021F80 135 KiB

- After the change:
RAM Usage 0E100000 - 0E167000 size 00067000 412 KiB 103 pages
.text 0E100000 - 0E108E48 size 00008E48 35 KiB
.rodata 0E108E48 - 0E10A3F0 size 000015A8 5 KiB
*hole* 0E10A3F0 - 0E10B000 size 00000C10 3 KiB
.data 0E10B000 - 0E10D278 size 00002278 8 KiB
*hole* 0E10D278 - 0E10D280 size 00000008 0 KiB
.bss 0E10D280 - 0E10FBE8 size 00002968 10 KiB
.heap1 0E10FBE8 - 0E110000 size 00000418 1 KiB
.nozi 0E110000 - 0E11D300 size 0000D300 52 KiB
.heap2 0E11D300 - 0E12D000 size 0000FD00 63 KiB
.text_init 0E12D000 - 0E133460 size 00006460 25 KiB
.rodata_init 0E133460 - 0E1342D0 size 00000E70 3 KiB
.rodata_pageable 0E1342D0 - 0E139A50 size 00005780 21 KiB
.text_pageable 0E139A50 - 0E167000 size 0002D5B0 181 KiB

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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ta/ta.mk: export CFG_TA_DYNLINK

Allows a TA to determine at build time if the targeted OP-TEE supports
run time dynamic linking.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Review

ta/ta.mk: export CFG_TA_DYNLINK

Allows a TA to determine at build time if the targeted OP-TEE supports
run time dynamic linking.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: support relocation type R_ARM_REL32

I have encounterd the relocation type R_ARM_REL32 in a shared library,
so implement it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

core: arm: support relocation type R_ARM_REL32

I have encounterd the relocation type R_ARM_REL32 in a shared library,
so implement it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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TA dev kit: shared library: add -f argument to ln

When creating a symbolic link <uuid>.elf -> libname.so, use the -f (force)
argument so that the command won't fail if the link already exists. It is

TA dev kit: shared library: add -f argument to ln

When creating a symbolic link <uuid>.elf -> libname.so, use the -f (force)
argument so that the command won't fail if the link already exists. It is
a very common case: the first time the library is built and the link is
created. Then whenever some source file is modified, the .so is re-linked
but the symbolic link is there already.

Fixes: 01b8b5ce011d ("TA dev kit: when building a shared library, create symlink with UUID")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

scripts/symbolize.py: print path of ELF files

Show which file corresponds to each ELF binary in a TA. Symbolic links
are followed, so that dynamic libraries are likely shown with their
user-friendly

scripts/symbolize.py: print path of ELF files

Show which file corresponds to each ELF binary in a TA. Symbolic links
are followed, so that dynamic libraries are likely shown with their
user-friendly name (libfoo.so) rather than their UUID (<uuid>.elf) --
see commit 01b8b5ce011d ("TA dev kit: when building a shared library,
create symlink with UUID").

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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pta: add system pTA

Add system pTA, which provides misc. auxiliary services, extending
existing GlobalPlatform Core API.
Add a call for seeding entropy to the default RNG pool.

Reviewed-by: Jens Wi

pta: add system pTA

Add system pTA, which provides misc. auxiliary services, extending
existing GlobalPlatform Core API.
Add a call for seeding entropy to the default RNG pool.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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synquacer: Add DeveloperBox platform support

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

core: fix TA_RAM_SIZE in generic RAM layout

TA_RAM_SIZE subtracts TEE_RAM_VA_SIZE twice, resulting in
a gap in the memory map. This restores the memory map to what
it was before the generic layout c

core: fix TA_RAM_SIZE in generic RAM layout

TA_RAM_SIZE subtracts TEE_RAM_VA_SIZE twice, resulting in
a gap in the memory map. This restores the memory map to what
it was before the generic layout change.

PLATFORM=stm-b2260

Macro Pre-Generic-Layout Post-Generic-Layout With-This-Fix
TZDRAM_BASE 7e000000 7e000000 7e000000
TZDRAM_SIZE 01c00000 01c00000 01c00000
TEE_RAM_VA_SIZE 00100000 00100000 00100000
TA_RAM_START 7e100000 7e100000 7e100000
RA_RAM_SIZE 01b00000 *01a00000* 01b00000
TEE_SHMEM_START 7fc00000 7fc00000 7fc00000

Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

scripts/symbolize.py: add support for dynamically linked TAs

Dynamically linked TAs contain sections mapped from several ELF files.
Update symbolize.py accordingly. As a result, the call stack will

scripts/symbolize.py: add support for dynamically linked TAs

Dynamically linked TAs contain sections mapped from several ELF files.
Update symbolize.py accordingly. As a result, the call stack will show
the expected debug information instead of "?? ??:0" for stack frames
that belong to a dynamic library. Also, the memory regions used to
map libraries will be annotated with section names like for the main
executable.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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TA dev kit: when building a shared library, create symlink with UUID

For convenience for use by tools such as scripts/symbolize.py, create
a symbolic link <uuid>.elf -> libfoo.so.

Signed-off-by: Je

TA dev kit: when building a shared library, create symlink with UUID

For convenience for use by tools such as scripts/symbolize.py, create
a symbolic link <uuid>.elf -> libfoo.so.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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libmbedtls: refine mbedtls license header

e0186224bba7 ("libmbedtls: refine mbedtls license header") from
branch import/mbedtls-2.6.1

New header format according to this:
https://github.com/OP-TEE/

libmbedtls: refine mbedtls license header

e0186224bba7 ("libmbedtls: refine mbedtls license header") from
branch import/mbedtls-2.6.1

New header format according to this:
https://github.com/OP-TEE/optee_os/blob/master/documentation/
copyright_and_license_headers.rst

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Edison Ai <edison.ai@arm.com>
[jw: removed the now redundant SPDX-License-Identifier]
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: add support for dynamically linked TAs

Adds the missing bits to be able to load 64-bit dynamically linked TAs.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by:

core: arm64: add support for dynamically linked TAs

Adds the missing bits to be able to load 64-bit dynamically linked TAs.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMUv8)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 32/64)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: elf_load_dyn.c: prepare for arm64 support

Use generic structures (elf_shdr, elf_dyn and elf_sym) rather than
ELF32-specific ones (Elf32_Shdr, Elf32_Dyn and Elf32_Sym) to process
dependencies a

core: elf_load_dyn.c: prepare for arm64 support

Use generic structures (elf_shdr, elf_dyn and elf_sym) rather than
ELF32-specific ones (Elf32_Shdr, Elf32_Dyn and Elf32_Sym) to process
dependencies and symbol resolution. This is a first step towards 64-bit
support.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...