libutils: asm.S: fix BTI() macro

The BTI() macro conditionally emits assembly instructions or directives
depending on CFG_CORE_BTI and CFG_TA_BTI configuration, but it doesn't
take ldelf into consid

libutils: asm.S: fix BTI() macro

The BTI() macro conditionally emits assembly instructions or directives
depending on CFG_CORE_BTI and CFG_TA_BTI configuration, but it doesn't
take ldelf into consideration. ldelf depends on CFG_CORE_BTI just as
OP-TEE core. Fix this by adding __LDELF__ to the mix.

Fixes: af432c48741c ("libutils: asm.S : Introduce BTI in macros for functions")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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libmbedtls: config: disable long long divisions

Currently on Aarch64, mbedtls uses long long divisions which result in
calls to __udivti3() in libgcc. This is at the moment the only
dependency on li

libmbedtls: config: disable long long divisions

Currently on Aarch64, mbedtls uses long long divisions which result in
calls to __udivti3() in libgcc. This is at the moment the only
dependency on libgcc in mbedtls, so disable the long long divisions by
defining MBEDTLS_NO_UDBL_DIVISION to remove the dependency.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked

drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: add sama7g5's PDMC gclk clocks to the SCMI clock list

Add PDMC gclk clocks to the SCMI clock list so that they could be
used outside OP-TEE OS.

Signed-off-by: Tony Han <tony.han@microchip

plat-sam: add sama7g5's PDMC gclk clocks to the SCMI clock list

Add PDMC gclk clocks to the SCMI clock list so that they could be
used outside OP-TEE OS.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69

drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set

drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set correct ID
to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ack

drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES com

drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES command.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_sc

plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_scmi_clock_rates_by_step()" to be used by SCMI.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci: add build of remote proc driver on stm32mp15

Remote proc driver is not build by default on stm32mp15.
Add CI rules to ensure the driver builds correctly.

Signed-off-by: Thomas Bourgoin <thomas.

ci: add build of remote proc driver on stm32mp15

Remote proc driver is not build by default on stm32mp15.
Add CI rules to ensure the driver builds correctly.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_remote_proc: fix definition of stm32_rproc_compat_data

Fix compilation error of core/drivers/remoteproc/stm32_remoteproc.c
Move bool ns_loading from "struct stm32_rproc_instance" to
"

drivers: stm32_remote_proc: fix definition of stm32_rproc_compat_data

Fix compilation error of core/drivers/remoteproc/stm32_remoteproc.c
Move bool ns_loading from "struct stm32_rproc_instance" to
"struct stm32_rproc_compat_data".

Fixes: a03044318866 ("drivers: stm32_remote_proc: add stm32_rproc_is_secure()")
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci: add S-EL0 SP tests to the BTI+MTE+PAC job

Enable S-EL0 SP tests for the S-EL1 SPMC with BTI+MTE+PAC enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier

ci: add S-EL0 SP tests to the BTI+MTE+PAC job

Enable S-EL0 SP tests for the S-EL1 SPMC with BTI+MTE+PAC enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: boot: add boot_init_primary_runtime()

Split the early parts of boot_init_primary_final() into
boot_init_primary_runtime(). boot_init_primary_runtime() initializes the
runtime, part of that is

core: boot: add boot_init_primary_runtime()

Split the early parts of boot_init_primary_final() into
boot_init_primary_runtime(). boot_init_primary_runtime() initializes the
runtime, part of that is to generate the PAUTH keys. The PAUTH keys are
loaded in assembly before boot_init_primary_final() is called.

This fixes an error when SPs are initialized by entering and exiting
S-EL0 from boot_init_primary_final() but the PAUTH registers hasn't been
initialized with the right values.
E/TC:0 0 Core undef-abort at address 0xe106be4
E/TC:0 0 esr 0x72000000 ttbr0 0x200000e27d000 ttbr1 0x00000000 cidr 0x0
E/TC:0 0 cpu #0 cpsr 0x60000144
E/TC:0 0 x0 0000000000000000 x1 0000000000000000
E/TC:0 0 x2 0000000000000000 x3 0000000000000000
E/TC:0 0 x4 000000000e27a060 x5 000000000e27a05c
E/TC:0 0 x6 000000000000009f x7 0000000000000083
E/TC:0 0 x8 0000000000000000 x9 0000000000004367
E/TC:0 0 x10 000000000000009f x11 0000000000000000
E/TC:0 0 x12 0000000000000000 x13 0000000040006f80
E/TC:0 0 x14 0000000000000000 x15 0000000000000000
E/TC:0 0 x16 000000000e107460 x17 0000000000000000
E/TC:0 0 x18 0000000000000000 x19 000000000e002000
E/TC:0 0 x20 000000000e300000 x21 0000000040000000
E/TC:0 0 x22 0000000000000000 x23 000000000e272830
E/TC:0 0 x24 000000000e22c250 x25 0000000000000000
E/TC:0 0 x26 0000000000000000 x27 0000000000000000
E/TC:0 0 x28 0000000000000000 x29 000000000e27a020
E/TC:0 0 x30 0a2ed3b10e1314e8 elr 000000000e106be4
E/TC:0 0 sp_el0 000000000e27a010
E/TC:0 0 TEE load address @ 0xe100000
E/TC:0 0 Core undef-abort at address 0xe106be4 .debug_info+27620
E/TC:0 0 Call stack:
E/TC:0 0 0x0e106be4 thread_enter_user_mode at core/arch/arm/kernel/thread.c:1049
E/TC:0 0 0x0e110628 sp_open_session at core/arch/arm/kernel/secure_partition.c:635
E/TC:0 0 0x0e112508 sp_init_uuid at core/arch/arm/kernel/secure_partition.c:1583
E/TC:0 0 0x0e1135f8 sp_init_all at core/arch/arm/kernel/secure_partition.c:2018
E/TC:0 0 0x0e137950 do_init_calls at core/kernel/initcall.c:20
E/TC:0 0 0x0e137b0c call_finalcalls at core/kernel/initcall.c:73

Fixes: b5ec8152f3e5 ("core: arm: refactor boot")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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libmbedtls: fix compilation warning with GCC14

GCC 14.2 outputs the following compilation warning:

CC out/arm-plat-imx/ta_arm64-lib/libmbedtls/mbedtls/library/ecp.o
In file included from lib/li

libmbedtls: fix compilation warning with GCC14

GCC 14.2 outputs the following compilation warning:

CC out/arm-plat-imx/ta_arm64-lib/libmbedtls/mbedtls/library/ecp.o
In file included from lib/libmbedtls/mbedtls/library/ctr_drbg.c:13:
In function ‘mbedtls_xor’,
inlined from ‘ctr_drbg_update_internal’ at lib/libmbedtls/mbedtls/library/ctr_drbg.c:372:5:
lib/libmbedtls/mbedtls/library/common.h:245:17: warning: array subscript 48 is outside array bounds of ‘unsigned char[48]’ [-Warray-bounds=]
245 | r[i] = a[i] ^ b[i];
| ~^~~
lib/libmbedtls/mbedtls/library/ctr_drbg.c: In function ‘ctr_drbg_update_internal’:
lib/libmbedtls/mbedtls/library/ctr_drbg.c:335:19: note: at offset 48 into object ‘tmp’ of size 48
335 | unsigned char tmp[MBEDTLS_CTR_DRBG_SEEDLEN];
| ^~~

Fix it by returning early in mbedtls_xor() if the compiler is GCC.
This fix is not in MBed TLS upstream yet but the issue and the fix have
been reported [1].

Link: https://github.com/Mbed-TLS/mbedtls/issues/9003#issuecomment-2108239255 [1]
Reported-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Closes: https://github.com/OP-TEE/optee_os/issues/7295
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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plat-rockchip: rk3588: Correct TZDRAM_START and SHMEM_START

Update the TZDRAM_START and SHMEM_START values to match the PX30 and
RK3399 values. If this is not done, a compressed kernel using the
def

plat-rockchip: rk3588: Correct TZDRAM_START and SHMEM_START

Update the TZDRAM_START and SHMEM_START values to match the PX30 and
RK3399 values. If this is not done, a compressed kernel using the
default value of kernel_comp_addr_r (0x0a000000) within U-Boot and
having a decompressed size greater than 28MiB puts the decompressed
kernel in the reserved address space for OP-TEE that starts at
0x08400000. Using the values for the RK3399 and PX30 avoids this
problem.

Fixes: 14754b93b1b7 ("plat-rockchip: add support for Rockchip rk3588")
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-rockchip: rk3588: Increase FDT Max Size to 384KiB

Increase the maximum size of the FDT to 384KiB to match the proposed
changes with Arm Trusted Firmware. This allows us to pass and parse
the FD

plat-rockchip: rk3588: Increase FDT Max Size to 384KiB

Increase the maximum size of the FDT to 384KiB to match the proposed
changes with Arm Trusted Firmware. This allows us to pass and parse
the FDT within OP-TEE. When doing this, we also need to allow OP-TEE
to detect the maximum PA bits so that allocating RAM above 4GiB does
not fail.

With these two changes, OP-TEE can parse and add the correct memory
nodes to the devicetree passed to it automatically.

Associated A-TF commit:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/34997

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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sign_encrypt.py: Fix typo from 'Unkown' to 'Unknown'

The value of enc_algo_name and flags_name was set to 'Unkown',
should be 'Unknown' instead.

Signed-off-by: Aristo Chen <aristo.chen@canonical.co

sign_encrypt.py: Fix typo from 'Unkown' to 'Unknown'

The value of enc_algo_name and flags_name was set to 'Unkown',
should be 'Unknown' instead.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: conf: default enable HASH

Default enable HASH compilation.
Enable CFG_STM32_CRYPTO_DRIVERS if any crypto IP is compiled.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>

plat-stm32mp1: conf: default enable HASH

Default enable HASH compilation.
Enable CFG_STM32_CRYPTO_DRIVERS if any crypto IP is compiled.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: enable HASH on stm32mp135f-dk

Sets HASH peripheral status to okay.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

crypto: stm32: use HASH IP for HASH and HMAC algorithm

Add HASH IP drivers, and add hooks in OP-TEE crypto framework to use
HASH IP to do HASH and HMAC process

Signed-off-by: Nicolas Toromanoff <ni

crypto: stm32: use HASH IP for HASH and HMAC algorithm

Add HASH IP drivers, and add hooks in OP-TEE crypto framework to use
HASH IP to do HASH and HMAC process

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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mk/compile.mk: add -undef and -D__DTS__ in dtb-cppflags

Commit 61b2d6e460f7 ("mk/compile.mk: add -Ulinux -Uunix to
dtb-cppflags") addresses some macro enabled by default by the
compiler that could i

mk/compile.mk: add -undef and -D__DTS__ in dtb-cppflags

Commit 61b2d6e460f7 ("mk/compile.mk: add -Ulinux -Uunix to
dtb-cppflags") addresses some macro enabled by default by the
compiler that could impact the pre-processing of the DTS files.

Instead of un-defining each of such macros, use the flag '-undef'
and get rid of all of them in one shot.

Add the macro '__DTS__' specific for DTS pre-processing, as it is
done in Linux and later ported to U-Boot with [1].
This could help sharing include files between DTS and C code.

Link: https://github.com/u-boot/u-boot/commit/f53932addd31 [1]
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: mm: Support dynamic allocation of translation tables

With CFG_DYN_CONFIG enabled allocate translation tables using the
boot_mem_*() functions. Static allocation from global variables is

core: riscv: mm: Support dynamic allocation of translation tables

With CFG_DYN_CONFIG enabled allocate translation tables using the
boot_mem_*() functions. Static allocation from global variables is still
used with CFG_DYN_CONFIG disabled.

This commit is referenced from ARM introduced in commit a28e4a0fe48d
("core: arm: mm: dynamic allocation of LPAE translation tables").

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: mm: Minor refactoring and add missing code

Add core_pos as argument of core_mmu_get_root_pgt_va() and clean up
relevant code. Add missing code of printing memory map into
core_init_mmu_

core: riscv: mm: Minor refactoring and add missing code

Add core_pos as argument of core_mmu_get_root_pgt_va() and clean up
relevant code. Add missing code of printing memory map into
core_init_mmu_prtn_tee().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: Add boot mem paddings to the heap

Add the paddings added due to requested alignment in boot mem
allocations to the heap.

This commit is referenced from ARM architecture introduced in c

core: riscv: Add boot mem paddings to the heap

Add the paddings added due to requested alignment in boot mem
allocations to the heap.

This commit is referenced from ARM architecture introduced in commit
0799b137207b ("core: arm: add boot mem paddings to the heap").

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: Implicitly enable CFG_BOOT_MEM

Now both ARM and RISC-V architectures support and enable CFG_BOOT_MEM by
default. It's unnecessary to define CFG_BOOT_MEM. This commit removes
CFG_BOOT_MEM and r

core: Implicitly enable CFG_BOOT_MEM

Now both ARM and RISC-V architectures support and enable CFG_BOOT_MEM by
default. It's unnecessary to define CFG_BOOT_MEM. This commit removes
CFG_BOOT_MEM and relevant dead code.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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