drivers: stm32_cpu_opp: skip OPP unsupported by SOC

Use device ID to remove not supported OPP.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@fos

drivers: stm32_cpu_opp: skip OPP unsupported by SOC

Use device ID to remove not supported OPP.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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dts: stm32: describe supported-hw on CPU OPP for STM32MP13

Describe supported hardware for each OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Etienne Carriere <etienne.carrie

dts: stm32: describe supported-hw on CPU OPP for STM32MP13

Describe supported hardware for each OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: chip and STM32MP15 platform identification

New platform function to get the chip identification using
DBGMCU SoC register.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>

plat-stm32mp1: chip and STM32MP15 platform identification

New platform function to get the chip identification using
DBGMCU SoC register.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: retrieve chip id from syscfg

Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.

Use the chip id to dynamically detect the CRYPTO hardware
support, the se

plat-stm32mp1: retrieve chip id from syscfg

Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.

Use the chip id to dynamically detect the CRYPTO hardware
support, the second CPU core, and CPU OPP.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_cpu_opp: skip OPP with unsupported voltage

Remove operating points that could not be handled
by the regulator supplying the CPU.

Signed-off-by: Patrick Delaunay <patrick.delaunay@fos

drivers: stm32_cpu_opp: skip OPP with unsupported voltage

Remove operating points that could not be handled
by the regulator supplying the CPU.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: default enable CFG_STM32_CPU_OPP for STM32MP13

Enable CFG_STM32_CPU_OPP for STM32MP13 and increase
CFG_STM32MP_OPP_COUNT to 3 OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.co

plat-stm32mp1: default enable CFG_STM32_CPU_OPP for STM32MP13

Enable CFG_STM32_CPU_OPP for STM32MP13 and increase
CFG_STM32MP_OPP_COUNT to 3 OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: describe CPU OPP for STM32MP13

Describe CPU operating points for STM32MP13 boards.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@fos

dts: stm32: describe CPU OPP for STM32MP13

Describe CPU operating points for STM32MP13 boards.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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drivers: add stm32 CPU DVFS driver

drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.

drivers: add stm32 CPU DVFS driver

drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.
It will be used by the SCMI performance service.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci: fix typo: CFG_TA_MEBDTLS_UNSAFE_MODEXP

CFG_TA_"MEBDTLS"_UNSAFE_MODEXP is typo. This commit fixes it.

Fixes: bb7ce54ecb3d ("ci: add arm64 job")
Signed-off-by: Alvin Chang <alvinga@andestech.com>

ci: fix typo: CFG_TA_MEBDTLS_UNSAFE_MODEXP

CFG_TA_"MEBDTLS"_UNSAFE_MODEXP is typo. This commit fixes it.

Fixes: bb7ce54ecb3d ("ci: add arm64 job")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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libmbedtls: fix typo: CFG_TA_MEBDTLS_UNSAFE_MODEXP

CFG_TA_"MEBDTLS"_UNSAFE_MODEXP is typo. This commit fixes it.

Fixes: cb03400251f9 ("Squashed commit upgrading to mbedtls-3.6.2")
Signed-off-by: Al

libmbedtls: fix typo: CFG_TA_MEBDTLS_UNSAFE_MODEXP

CFG_TA_"MEBDTLS"_UNSAFE_MODEXP is typo. This commit fixes it.

Fixes: cb03400251f9 ("Squashed commit upgrading to mbedtls-3.6.2")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: boot: fix calling page_alloc_init()

The functions page_alloc_init() and nex_page_alloc_init() depends on
MEM_AREA_TEE_DYN_VASPACE and MEM_AREA_NEX_DYN_VASPACE, but the memory
areas are on

core: arm: boot: fix calling page_alloc_init()

The functions page_alloc_init() and nex_page_alloc_init() depends on
MEM_AREA_TEE_DYN_VASPACE and MEM_AREA_NEX_DYN_VASPACE, but the memory
areas are only available with CFG_DYN_CONFIG so check that before
calling the functions.

Fixes: 0e12fb0c2d75 ("core: arm: boot: call page_alloc_init()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix CFG_BOOT_INIT_THREAD_CORE_LOCAL0

CFG_BOOT_INIT_THREAD_CORE_LOCAL0 is misleading since it's concerning the
core id of the boot CPU. So rename the configuration flag to
CFG_BOOT_INIT_CURRENT

core: fix CFG_BOOT_INIT_THREAD_CORE_LOCAL0

CFG_BOOT_INIT_THREAD_CORE_LOCAL0 is misleading since it's concerning the
core id of the boot CPU. So rename the configuration flag to
CFG_BOOT_INIT_CURRENT_THREAD_CORE_LOCAL and update the code as needed.
Only thread_init_thread_core_local() has a change of behaviour where the
boot CPU now can have any core id.

Fixes: b5ec8152f3e5 ("core: arm: refactor boot")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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scripts: sign_rproc_fw: Add the support of encrypted signature key

Add possibility to provide a passphrase for an encrypted PEM key
used for the signature.

The passphrase is provided with the optio

scripts: sign_rproc_fw: Add the support of encrypted signature key

Add possibility to provide a passphrase for an encrypted PEM key
used for the signature.

The passphrase is provided with the optional --key_pwd argument.

usage:
--key_pwd="my password"

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: stm32: disable unused i2c1 and i2c2

i2c1 and i2c2 on Avenger96 board are not consumed by OP-TEE,
therefore they can be disabled.

Link: https://github.com/OP-TEE/optee_os/issues/7296
Acked-by:

dts: stm32: disable unused i2c1 and i2c2

i2c1 and i2c2 on Avenger96 board are not consumed by OP-TEE,
therefore they can be disabled.

Link: https://github.com/OP-TEE/optee_os/issues/7296
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Daniel Lang <ldaniell14260@gmail.com>

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core: arm: boot: call page_alloc_init()

Call page_alloc_init()/nex_page_alloc_init() from init_primary() after
unused boot memory has been released. virt_guest_created() calls
page_alloc_init().

Th

core: arm: boot: call page_alloc_init()

Call page_alloc_init()/nex_page_alloc_init() from init_primary() after
unused boot memory has been released. virt_guest_created() calls
page_alloc_init().

This allows virt_page_alloc() to be used instead of boot_mem_alloc() now
that boot_mem_alloc() can't be used any longer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: add virt_page_alloc()

Add virt_page_alloc() to allocate memory from physical pool and map it
in a virtual address pool.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-

core: mm: add virt_page_alloc()

Add virt_page_alloc() to allocate memory from physical pool and map it
in a virtual address pool.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: add phys_mem_alloc_flags()

Add phys_mem_alloc_flags() taking MAF_* flags to control memory
allocation. The new flag MAF_CORE_MEM behaves like
{nex_,}phys_mem_core_alloc(), if the flag is

core: mm: add phys_mem_alloc_flags()

Add phys_mem_alloc_flags() taking MAF_* flags to control memory
allocation. The new flag MAF_CORE_MEM behaves like
{nex_,}phys_mem_core_alloc(), if the flag is absent it becomes
{nex_,}phys_mem_ta_alloc().

The MAF_NEX flag selects Nexus memory.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add tee_mm_alloc_flags()

Add tee_mm_alloc_flags() taking a flags field to passed to
malloc_flags() when allocating the tee_mm_entry_t.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org

core: add tee_mm_alloc_flags()

Add tee_mm_alloc_flags() taking a flags field to passed to
malloc_flags() when allocating the tee_mm_entry_t.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: tee_mm.c: use malloc_flags() and free_flags()

Use malloc_flags() and free_flags() to simplify memory allocations
with regards to the MAF_NEX/TEE_MM_POOL_NEX_MALLOC flag.

Signed-off-by: Jens W

core: tee_mm.c: use malloc_flags() and free_flags()

Use malloc_flags() and free_flags() to simplify memory allocations
with regards to the MAF_NEX/TEE_MM_POOL_NEX_MALLOC flag.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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Use malloc flags MAF_* in tee_mm.h

Switch to use the malloc flags MAF_* in tee_mm.h replacing the previous
TEE_MM_POOL_* flags. TEE_MM_POOL_* flags are kept defined using MAF_*
flags to for easier t

Use malloc flags MAF_* in tee_mm.h

Switch to use the malloc flags MAF_* in tee_mm.h replacing the previous
TEE_MM_POOL_* flags. TEE_MM_POOL_* flags are kept defined using MAF_*
flags to for easier transition. The TEE_MM_POOL_* flags can be moved
gradually after this commit.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add nex_dyn_vaspace and tee_dyn_vaspace areas

Add MEM_AREA_NEX_DYN_VASPACE and MEM_AREA_TEE_DYN_VASPACE areas for
dynamic Nexus and TEE memory mapping. This will be used to map
additional heap

core: add nex_dyn_vaspace and tee_dyn_vaspace areas

Add MEM_AREA_NEX_DYN_VASPACE and MEM_AREA_TEE_DYN_VASPACE areas for
dynamic Nexus and TEE memory mapping. This will be used to map
additional heap and the stacks in later patches.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mmu: fix dynamic VA region dummy mapping

The commit 873f5f6c7201 ("core: mmu: Add dynamic VA regions' mapping to
page table") populated page tables so all are available later when
needed. Howe

core: mmu: fix dynamic VA region dummy mapping

The commit 873f5f6c7201 ("core: mmu: Add dynamic VA regions' mapping to
page table") populated page tables so all are available later when
needed. However, it also mapped physical address 0 in all those ranges.
So fix this by setting attributes to 0 when the physical address is 0.

Fixes: 873f5f6c7201 ("core: mmu: Add dynamic VA regions' mapping to page table")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: remove test on CFG_DRIVERS_GPIO

Remove test on CFG_DRIVERS_GPIO inside stm32_gpio.c C source file.
CFG_* dependencies are addressed in makefile file (e.g. plat-*/conf.mk),
not i

drivers: stm32_gpio: remove test on CFG_DRIVERS_GPIO

Remove test on CFG_DRIVERS_GPIO inside stm32_gpio.c C source file.
CFG_* dependencies are addressed in makefile file (e.g. plat-*/conf.mk),
not in the driver source file.

Fixes: 1001585e2e56 ("drivers: stm32_gpio: remove GPIO access specific API functions")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Deprecate libgcc for TAs

By default keep linking with libgcc for TAs, but add CFG_TA_LIBGCC to
easily turn off linking with libgcc in configurations where it isn't
needed.

Signed-off-by: Jens Wikla

Deprecate libgcc for TAs

By default keep linking with libgcc for TAs, but add CFG_TA_LIBGCC to
easily turn off linking with libgcc in configurations where it isn't
needed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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Deprecate libgcc for OP-TEE core and ldelf

By default turn of linking with ligcc for OP-TEE core and ldelf. This
allows building CFG_CORE_BTI=y and CFG_TA_BTI=n using a AArch64 cross
toolchain witho

Deprecate libgcc for OP-TEE core and ldelf

By default turn of linking with ligcc for OP-TEE core and ldelf. This
allows building CFG_CORE_BTI=y and CFG_TA_BTI=n using a AArch64 cross
toolchain without BTI enabled in libgcc.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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