| 6932fae7 | 03-May-2022 |
Andrew Davis <afd@ti.com> |
plat-k3: drivers: ti-sci: Add support for setting device state
This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.
Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Jerome Foriss
plat-k3: drivers: ti-sci: Add support for setting device state
This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.
Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 3efc0997 | 09-Jul-2020 |
Dhananjay Phadke <dphadke@linux.microsoft.com> |
scripts: use python's hex() in ta_bin_to_c.py
- Python has a built in function to turn a byte into its respective hex value that can be used instead of string formatting the values directly. - U
scripts: use python's hex() in ta_bin_to_c.py
- Python has a built in function to turn a byte into its respective hex value that can be used instead of string formatting the values directly. - Using the built in function instead of the previous string formatting method fixed an issue where bytes were failing to be written when we used an archaic yocto bsp from broadcom. - The built in function also has the benefit of being easier to read and understand.
Signed-off-by: Dhananjay Phadke <dphadke@linux.microsoft.com> Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 488c73c0 | 08-Jun-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: clk: remove stm32_clock_*() helpers
Removes function that were deprecated: stm32_clock_is_enabled(), stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().
Signed-off-by:
drivers: clk: remove stm32_clock_*() helpers
Removes function that were deprecated: stm32_clock_is_enabled(), stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| c8e35c97 | 09-Jun-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: armv7: fix ASLR error
With commit 528dabb28254 ("core: suppress text relocation on stack_tmp_export") the stack pointer is calculated using a relative address instead of based on an absolute a
core: armv7: fix ASLR error
With commit 528dabb28254 ("core: suppress text relocation on stack_tmp_export") the stack pointer is calculated using a relative address instead of based on an absolute address which is relocated with ASLR enabled.
Prior to this on Armv7 we compensate for a relocation update for stack_tmp_export_rel in reset_secondary() just after the stack pointer was initialized. So now when the relocation update of stack_tmp_export_rel is gone remove the compensating code too.
Fixes: 528dabb28254 ("core: suppress text relocation on stack_tmp_export") Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c36d2192 | 09-May-2022 |
Balint Dobszay <balint.dobszay@arm.com> |
core: sp: handle memory regions w/o base address
The FF-A spec states that in the SP manifest a base address is not mandatory for memory regions. If the field is not present, the specified memory re
core: sp: handle memory regions w/o base address
The FF-A spec states that in the SP manifest a base address is not mandatory for memory regions. If the field is not present, the specified memory region must be allocated by the SPMC and mapped to the SP's context.
A copy of the SP manifest fdt is used for passing the memory region virtual addresses to the SP. Additional space is allocated when copying the fdt so the originally not present base address fields can be added later.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> [jf: edit description to avoid checkpatch spelling warning] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 5a923b99 | 13-May-2022 |
Balint Dobszay <balint.dobszay@arm.com> |
core: sp: map memory regions from SP manifest
Currently the SP manifest processing only handles the device regions, add support to handle the normal memory regions too.
Note: if the region's base a
core: sp: map memory regions from SP manifest
Currently the SP manifest processing only handles the device regions, add support to handle the normal memory regions too.
Note: if the region's base address is a PA, according to the FF-A spec it has to be identity mapped to the same VA. This requirement will be removed in the spec's next version, so the current implementation should be acceptable.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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| 3da1a076 | 13-May-2022 |
Balint Dobszay <balint.dobszay@arm.com> |
core: sp: refactor manifest attribute checks
Simplify memory access attribute checks when parsing the SP manifest.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <e
core: sp: refactor manifest attribute checks
Simplify memory access attribute checks when parsing the SP manifest.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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| 65ef988f | 06-May-2022 |
Balint Dobszay <balint.dobszay@arm.com> |
core: sp: reorganize init functions
Move some of the SP init functions to prepare for the needed order in the upcoming patches. This change doesn't modify functionality.
Acked-by: Jens Wiklander <j
core: sp: reorganize init functions
Move some of the SP init functions to prepare for the needed order in the upcoming patches. This change doesn't modify functionality.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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| b97479cb | 08-Jun-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: se050: scp: add support for more boards
Add the board specific persistent keys required to stablish the SCP03 sessions with the secure element.
See https://www.nxp.com/docs/en/application-
drivers: se050: scp: add support for more boards
Add the board specific persistent keys required to stablish the SCP03 sessions with the secure element.
See https://www.nxp.com/docs/en/application-note/AN12436.pdf
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dc0db863 | 08-Jun-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: pm: sam: clarify that the pm_suspend.S file was relicensed
Clarify that this file was imported from Linux and relicensed to avoid any licensing issue.
Acked-by: Nicolas Ferre <nicolas.ferr
drivers: pm: sam: clarify that the pm_suspend.S file was relicensed
Clarify that this file was imported from Linux and relicensed to avoid any licensing issue.
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 3ab148c8 | 15-Apr-2022 |
Jerome Forissier <jerome.forissier@linaro.org> |
plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y
Enables Arm Cryptography Extensions by default for the rk3399 SoC since they are supported [1].
Link: [1] http://opensource.rock-chips.com/images/
plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y
Enables Arm Cryptography Extensions by default for the rk3399 SoC since they are supported [1].
Link: [1] http://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b917d42e | 10-May-2022 |
Igor Opaniuk <igor.opaniuk@foundries.io> |
zynqmp: platform: provide uart configuration during compilation
Add possibility to provide UART configuration as a compile flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).
Acked-by: Jerome Foris
zynqmp: platform: provide uart configuration during compilation
Add possibility to provide UART configuration as a compile flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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| 2ac060b7 | 01-Jun-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-vexpress: juno: default enable hwrng from smccc trng interface
Changes juno default configuration to get random bytes from TF-A SMCCC TRNG interface instead of the pseudo-RNG support form OP-TE
plat-vexpress: juno: default enable hwrng from smccc trng interface
Changes juno default configuration to get random bytes from TF-A SMCCC TRNG interface instead of the pseudo-RNG support form OP-TEE.
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno) Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 0347e53f | 17-May-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: smccc_trng: get entropy from secure monitor
Implements random noise generation interface from Arm SMCCC TRNG specification. Configuration switch CFG_ARM_SMCCC_TRNG must be enabled to embed
drivers: smccc_trng: get entropy from secure monitor
Implements random noise generation interface from Arm SMCCC TRNG specification. Configuration switch CFG_ARM_SMCCC_TRNG must be enabled to embed the RNG driver that use this interface.
When CFG_ARM_SMCCC_TRNG is enable and CFG_WITH_SOFTWARE_PRNG is disable, use SMCCC TRNG driver as entropy source. When both CFG_ARM_SMCCC_TRNG and CFG_WITH_SOFTWARE_PRNG are enable, seed OP-TEE PRNG with 32byte of TRNG entropy.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 98ba0dc3 | 17-May-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: arm: declare struct mobj in thread_arch.h
Adds missing declaration of struct mobj in arm/kernel/thread_arch.h.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne C
core: arm: declare struct mobj in thread_arch.h
Adds missing declaration of struct mobj in arm/kernel/thread_arch.h.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 4ebbfa74 | 02-May-2022 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: enable CFG_ATMEL_TCB
Enable CFG_ATMEL_TCB to use the TCB as a time source instead of CFG_SECURE_TIME_SOURCE_REE.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Cl
plat-sam: enable CFG_ATMEL_TCB
Enable CFG_ATMEL_TCB to use the TCB as a time source instead of CFG_SECURE_TIME_SOURCE_REE.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| d922c314 | 23-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: add timer clock driver
Add support for the TCB block that are present on the samad2. This series add support for the TCB as a time source and register it using REGISTER_TIME_SOURCE(). More
plat-sam: add timer clock driver
Add support for the TCB block that are present on the samad2. This series add support for the TCB as a time source and register it using REGISTER_TIME_SOURCE(). Moreover, on Linux, the tick is done using the TCB since the sama5d2 does not have the ARM architected timers. Since the time source used for the tick clocksource is probed early in the boot process, the SCMI clock support which uses a platform driver is not yet probed and thus the TCB can't be probe properly. To workaround that problem, this driver enables the TCB clocks and the Linux device-tree is modified to use "fixed-clock" clock instead of the TCB SCMI ones.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 90040fa4 | 06-May-2022 |
Sohaib ul Hassan <sohaib.ul.hassan@unikie.com> |
core: crypto: add X25519 support
This adds the X25519 core functionality and enables support for Curve25519 key attribute type for OP-TEE crypto syscalls.
Acked-by: Etienne Carriere <etienne.carrie
core: crypto: add X25519 support
This adds the X25519 core functionality and enables support for Curve25519 key attribute type for OP-TEE crypto syscalls.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Sohaib ul Hassan <sohaib.ul.hassan@unikie.com>
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| 2d7740f6 | 03-Jun-2022 |
Sohaib ul Hassan <sohaib.ul.hassan@unikie.com> |
core: libtomcrypt: Remove prng_state* NULL pointer check from x25519_make_key()
Calling x25519_make_key(prng_state *prng, int wprng, curve25519_key *key) checks if prng_state is NULL. This would req
core: libtomcrypt: Remove prng_state* NULL pointer check from x25519_make_key()
Calling x25519_make_key(prng_state *prng, int wprng, curve25519_key *key) checks if prng_state is NULL. This would require the caller to pass a valid pointer. Initializing prng_state in some configurations can get very large. For instance, xtest for X25519 key generation causes the TA to panic due to stack overrun
F/TC:? 0 trace_syscall:151 syscall #54 (syscall_obj_generate_key) E/TC:1 Dead canary at end of 'stack_abt[3]' (0xe1a01fc) E/TC:1 Panic at core/kernel/thread.c:124 <thread_check_canaries> E/TC:1 TEE load address @ 0xe100000 E/TC:1 Call stack: E/TC:1 0x0e108934 print_kernel_stack at optee_os/core/arch/arm/kernel/unwind_arm64.c:80 E/TC:1 0x0e113f24 __do_panic at optee_os/core/kernel/panic.c:24 E/TC:1 0x0e116eb4 thread_check_canaries at optee_os/core/kernel/thread.c:115 E/TC:1 0x0e106a60 thread_handle_std_smc at optee_os/core/arch/arm/kernel/thread_optee_smc.c:56
OP-TEE registers a custom prng descriptor (prng_crypto_desc) used for LTC asymmetric crypto operations and prng_state is not used.
The LTC_ARGCHK(prng != NULL) check is not present in the LTC key generation functions for ECC, RSA, DH and DSA implementations.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Sohaib ul Hassan <sohaib.ul.hassan@unikie.com>
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| 15cb2782 | 06-May-2022 |
Sohaib ul Hassan <sohaib.ul.hassan@unikie.com> |
core: libtomcrypt: Add X25519 support
This enables the X25519 implementation of libtomcrypt and adds the OP-TEE wrapper function definitions
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
core: libtomcrypt: Add X25519 support
This enables the X25519 implementation of libtomcrypt and adds the OP-TEE wrapper function definitions
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Sohaib ul Hassan <sohaib.ul.hassan@unikie.com>
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| 3f61056d | 06-May-2022 |
Sohaib ul Hassan <sohaib.ul.hassan@unikie.com> |
libutee: add X25519 support
This commit adds X25519 support to libutee as defined in TEE Internal Core API v1.2.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier
libutee: add X25519 support
This commit adds X25519 support to libutee as defined in TEE Internal Core API v1.2.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Sohaib ul Hassan <sohaib.ul.hassan@unikie.com> [jf: minor edit to commit description] Signed-off-by: Jerome Forissier <jerone.forissier@linaro.org>
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| d83a652a | 05-Aug-2019 |
Andrew Davis <afd@ti.com> |
plat-ti: Remove extra license text as we have SPDX
No functional change here.
Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> |
| b04758f2 | 29-Apr-2022 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: enable CFG_ATMEL_PIOBU by default
By default, enable CFG_ATMEL_PIOBU driver on plat-sam.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.foriss
plat-sam: enable CFG_ATMEL_PIOBU by default
By default, enable CFG_ATMEL_PIOBU driver on plat-sam.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 1fe98f82 | 11-Jan-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: atmel_piobu: add driver
Add piobu driver which handle secumod GPIOs. This driver also handle tampering interrupts on GPIOs which are configured as input with the device-tree. For instance,
drivers: atmel_piobu: add driver
Add piobu driver which handle secumod GPIOs. This driver also handle tampering interrupts on GPIOs which are configured as input with the device-tree. For instance, the following device-tree excerpt allows to set an input as an intrusion detection pin:
gpios = <0 PIOBU_PIN_INPUT(1, 1, PIOBU_PIN_PULL_DOWN, PIOBU_PIN_DEF_LEVEL_LOW, PIOBU_PIN_WAKEUP_ENABLE)>;
In case of a tamper event, the source of the tampering will be displayed.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| b2e4b77e | 29-Apr-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: atmel_rtc: add atmel_rtc_get_tamper_timestamp()
The sama5d2 RTC actually hold the timestamp of the last tampering attempt. Add a function to get the last time of tampering detection.
Acked
drivers: atmel_rtc: add atmel_rtc_get_tamper_timestamp()
The sama5d2 RTC actually hold the timestamp of the last tampering attempt. Add a function to get the last time of tampering detection.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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