dt-bindings: mfd: dual licensing for st,stpmic1 bindings

Change include/dt-bindings/mfd/st,stpmic1.h license model from GPLv2.0
only to dual GPLv2.0 or BSD-2-Clause. This change clarifies that
this

dt-bindings: mfd: dual licensing for st,stpmic1 bindings

Change include/dt-bindings/mfd/st,stpmic1.h license model from GPLv2.0
only to dual GPLv2.0 or BSD-2-Clause. This change clarifies that
this DT binding header file can be shared with software components as
bootloaders and OSes that are not published under GPLv2 terms as
OP-TEE OS is.

This change has been discussed and acked in the LKML [1].

Fixes: 1183a0aa2af0 ("stm32mp1: update DTS files to Linux kernel 5.2-rc1")
Link: https://lore.kernel.org/lkml/171941721004.2530174.778562710266249921.b4-ty@kernel.org/ [1]
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ffa: Improve FF-A memory sharing compliance

* Deny memory regions with zero pages
* Validate total page count field
* Validate total descriptor size including memory regions descriptors
* Fix

core: ffa: Improve FF-A memory sharing compliance

* Deny memory regions with zero pages
* Validate total page count field
* Validate total descriptor size including memory regions descriptors
* Fix incorrect FFA_ERROR status codes

Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: Deny unsupported memory sharing operations

Fragmented memory sharing operations and memory sharing where the
transaction descriptors are forwarded in a custom buffer are not
supported for

core: ffa: Deny unsupported memory sharing operations

Fragmented memory sharing operations and memory sharing where the
transaction descriptors are forwarded in a custom buffer are not
supported for SP destinations. Return early FFA_ERROR if these
conditions are detected.
Add CFG_NS_VIRTUALIZATION condition for virt_unset_guest calls in
thread_spmc.c as a minor refactoring step.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: Return transaction type flag in retrieve response

Setting 'Memory management transaction type flag' in memory transaction
descriptor when returned in FFA_MEM_RETRIEVE_RESP.

Signed-off-by

core: ffa: Return transaction type flag in retrieve response

Setting 'Memory management transaction type flag' in memory transaction
descriptor when returned in FFA_MEM_RETRIEVE_RESP.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: st: add RCC support on stm32mp257f-ev1

Configure the clock tree for stm32mp257f-ev1 board.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etien

dts: st: add RCC support on stm32mp257f-ev1

Configure the clock tree for stm32mp257f-ev1 board.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: st: enable RCC driver in stm32mp251

Add the RCC node to support clock on stm32mp25 platform.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <eti

dts: st: enable RCC driver in stm32mp251

Add the RCC node to support clock on stm32mp25 platform.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: rstctrl: add reset controller for STM32MP25 platforms

Implement the STM32MP25 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.

Signed-off-by: G

drivers: rstctrl: add reset controller for STM32MP25 platforms

Implement the STM32MP25 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rstctrl: move stm32mp1x controller in stm32mp1_rstcrl.c

This change prepares the STM32MP25 reset controller driver.
The binding for the STM32MP25 is different from that of the
STM32MP

drivers: stm32_rstctrl: move stm32mp1x controller in stm32mp1_rstcrl.c

This change prepares the STM32MP25 reset controller driver.
The binding for the STM32MP25 is different from that of the
STM32MP1x, so we will create a stm32mp25_rstcrl.c file.
This change factorizes STM32 API functions in stm32_rstcrl.c file
for probing and passing platform data.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st

clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add the STM32MP2 clock and reset bindings

Add the associated bindings for device tree and drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Ca

dt-bindings: add the STM32MP2 clock and reset bindings

Add the associated bindings for device tree and drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: add rcc helper function

Add dedicate include file for RCC to add helper function.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etie

plat-stm32mp2: add rcc helper function

Add dedicate include file for RCC to add helper function.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: sysconfig: add Safe Reset functionality

Add possibility to manage safely master IP reset.
This is managed in SYSCFG safe reset control register (SYSCFG_SAFERSTCR)

Signed-off-by: Gabr

plat-stm32mp2: sysconfig: add Safe Reset functionality

Add possibility to manage safely master IP reset.
This is managed in SYSCFG safe reset control register (SYSCFG_SAFERSTCR)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: add stm32mp25 sysconfig driver

Driver to manage system configuration (sysconf) registers
the sysconf are identified by an ID to be able to be adapted for DT.

Signed-off-by: Arnaud Po

plat-stm32mp2: add stm32mp25 sysconfig driver

Driver to manage system configuration (sysconf) registers
the sysconf are identified by an ID to be able to be adapted for DT.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: enable shared io driver

Default enable shared io driver for platform stm32mp2.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <e

plat-stm32mp2: conf: enable shared io driver

Default enable shared io driver for platform stm32mp2.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: add CFG_PGT_CACHE_ENTRIES

Add CFG_PGT_CACHE_ENTRIES to allow platforms to customize the page
table cache size. This is needed for example when a platform is to
support very large TAs of se

core: mm: add CFG_PGT_CACHE_ENTRIES

Add CFG_PGT_CACHE_ENTRIES to allow platforms to customize the page
table cache size. This is needed for example when a platform is to
support very large TAs of several dozen of Mbytes of private memory
(code/data).

Move PGT_CACHE_SIZE macro definition from pgt_cache.h to pgt_cache.c
since it is used only in that source file.

By the way, fix pgt_cache.h layout to have header files includes first
followed by macro definitions.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Squashed commit upgrading to mbedtls-3.6.0

Squash merging branch import/mbedtls-3.6.0

0fc9291f4 ("libmbedtls: bignum: restore mbedtls_mpi_exp_mod() from v3.5.2")
0ef87b1e6 ("libmbedtls: reset minim

Squashed commit upgrading to mbedtls-3.6.0

Squash merging branch import/mbedtls-3.6.0

0fc9291f4 ("libmbedtls: bignum: restore mbedtls_mpi_exp_mod() from v3.5.2")
0ef87b1e6 ("libmbedtls: reset minimum rsa key size")
70b079496 ("libmbedtls: adjust use of rsa pk_wrap API")
6cf76464f ("libmbedtls: allow inclusion of arm_neon.h")
27df5c911 ("libmbedtls: fix cipher_wrap.c for NIST AES Key Wrap mode")
aa584f9ed ("libmbedtls: fix cipher_wrap.c for chacha20 and chachapoly")
523ae957e ("libmbedtls: add fault mitigation in mbedtls_rsa_rsassa_pkcs1_v15_verify()")
30bdb1bbf ("libmbedtls: add fault mitigation in mbedtls_rsa_rsassa_pss_verify_ext()")
e45cdab62 ("libmbedtls: add SM2 curve")
d2fda4fc2 ("libmbedtls: fix no CRT issue")
ab0eb5515 ("libmbedtls: add interfaces in mbedtls for context memory operation")
7925a6f26 ("libmedtls: mpi_miller_rabin: increase count limit")
8eaf69279 ("libmbedtls: add mbedtls_mpi_init_mempool()")
12e83fc8d ("libmbedtls: make mbedtls_mpi_mont*() available")
f9e261da5 ("mbedtls: configure mbedtls to reach for config")
7b6f378d7 ("mbedtls: remove default include/mbedtls/config.h")
c16331743 ("Import mbedtls-3.6.0")

Signed-off-by: Tom Van Eyck <tom.vaneyck@kuleuven.be>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: pass TEE_ATTR_RSA_OAEP_MGF_HASH to RSA-OAEP implementations

OP-TEE currently doesn't support using a different hash for MGF1
with RSA-OAEP. However, this is required for AOSP compatibility
(e.

core: pass TEE_ATTR_RSA_OAEP_MGF_HASH to RSA-OAEP implementations

OP-TEE currently doesn't support using a different hash for MGF1
with RSA-OAEP. However, this is required for AOSP compatibility
(e.g. in EncryptionOperationsTest.RsaOaepWithMGFDigestSuccess [1]).

Pass the MGF1 attribute to crypto implementations. Note that
only libtomcrypt supports this feature at the moment, so other
implementations will either fail or fall back to libtomcrypt when
passed a different MGF1 hash.

Link: https://android.googlesource.com/platform/hardware/interfaces/+/refs/heads/main/security/keymint/aidl/vts/functional/KeyMintTest.cpp#5552 [1]
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: register CPU OPP clock for SCMI usage

Add the definitinon for 'AT91_SCMI_CLK_CPU_OPP'.
When the CPU OPP clock is available, add it to SCMI clock list.

Signed-off-by: Tony Han <tony.han@mi

plat-sam: register CPU OPP clock for SCMI usage

Add the definitinon for 'AT91_SCMI_CLK_CPU_OPP'.
When the CPU OPP clock is available, add it to SCMI clock list.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add the implement of CPU OPP clock

Register CPU OPP clock with the following operations:
- set_rate: call the operation of its parent
- get_rates_array: return the rates got fro

drivers: clk: sam: add the implement of CPU OPP clock

Register CPU OPP clock with the following operations:
- set_rate: call the operation of its parent
- get_rates_array: return the rates got from DT.
Skip CPU OPP clock register when OPP is not supported.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: prepare for CPU OPP (Operating Performance Points) support

Initialize clock rates array by parsing the device tree.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carr

plat-sam: prepare for CPU OPP (Operating Performance Points) support

Initialize clock rates array by parsing the device tree.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: at91: add assigned-clock settings for sama7g5 qspi0

Assign QSPI0's clock to SYSPLL GCK 133MHz.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@fos

dts: at91: add assigned-clock settings for sama7g5 qspi0

Assign QSPI0's clock to SYSPLL GCK 133MHz.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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scripts: fix invalid escape sequence

A backslash-character pair that is not a valid
escape sequence is generating a SyntaxWarning in
Python 3.12 and could generate a SyntaxError in a
future version.

scripts: fix invalid escape sequence

A backslash-character pair that is not a valid
escape sequence is generating a SyntaxWarning in
Python 3.12 and could generate a SyntaxError in a
future version.

Use a raw string to avoid the escape.

Signed-off-by: Shen Jiamin <shen_jiamin@comp.nus.edu.sg>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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plat-mediatek: add support to extend MAX_XLAT_TABLE

When using the reserved virtual memory space, it is necessary to
increase MAX_XLAT_TABLE based on its size.

Signed-off-by: Gavin Liu <gavin.liu@m

plat-mediatek: add support to extend MAX_XLAT_TABLE

When using the reserved virtual memory space, it is necessary to
increase MAX_XLAT_TABLE based on its size.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ree_fs: fix dirfile handle refcount

The counter ree_fs_dirh_refcount is used to determine when ree_fs_dirh
should be free, not as a guarantee that ree_fs_dirh is still valid. This
wasn't the a

core: ree_fs: fix dirfile handle refcount

The counter ree_fs_dirh_refcount is used to determine when ree_fs_dirh
should be free, not as a guarantee that ree_fs_dirh is still valid. This
wasn't the assumption in ree_fs_readdir_rpc(), ree_fs_closedir_rpc(),
and ree_fs_opendir_rpc(). So fix that by using get_dirh() in
ree_fs_readdir_rpc as needed.

Reported-by: Gavin Liu <gavin.liu@mediatek.com>
Closes: https://github.com/OP-TEE/optee_os/issues/6895
Fixes: ace6039fd434 ("core: REE_FS: refcount dirfile handle")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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libutils, zlib: fix Clang warnings

Clang 18.1.6 reports the following warnings:

CC out/arm/ldelf-lib/libutils/isoc/bget_malloc.o
In file included from lib/libutils/isoc/bget_malloc.c:127:

libutils, zlib: fix Clang warnings

Clang 18.1.6 reports the following warnings:

CC out/arm/ldelf-lib/libutils/isoc/bget_malloc.o
In file included from lib/libutils/isoc/bget_malloc.c:127:
lib/libutils/isoc/bget.c:607:7: warning: a function definition without a prototype is deprecated in all versions of C and is not supported in C23 [-Wdeprecated-non-prototype]
607 | void *bget(requested_align, hdr_size, requested_size, poolset)
| ^

And same with lib/zlib/{adler32.c,inffast.c,inflate.c,zutil.c}.

In addition, zutil.c causes:

CC out/arm/core/lib/zlib/zutil.o
core/lib/zlib/zutil.c:28:33: warning: a function declaration without a prototype is deprecated in all versions of C [-Wstrict-prototypes]
28 | const char * ZEXPORT zlibVersion()
| ^
| void

Add -Wno-deprecated-non-prototype to libutils' bget_malloc.c to silence
the first series, and simply remove -Wstrict-prototypes (added by
default by mk/compile.mk) when building zlib.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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