drivers: scmi-msg: fix clock rates description remaining count

Fix value of remaining clocks to describe on SCMI clock protocol
message CLOCK_DESCRIBE_RATES that does not take into account the
numbe

drivers: scmi-msg: fix clock rates description remaining count

Fix value of remaining clocks to describe on SCMI clock protocol
message CLOCK_DESCRIBE_RATES that does not take into account the
number of returned clock in the response.

Fixes: 90252e2a52c7 ("drivers: scmi-msg: clock adapts to output buffer size")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: scmi-msg: correct voltage domain protocol version

Fix the version ID of the implemented SCMI voltage domain protocol that
is v2.0 (ID 0x20000), not v3.0 (ID 0x30000).

Fixes: 006d89b8f49f (

drivers: scmi-msg: correct voltage domain protocol version

Fix the version ID of the implemented SCMI voltage domain protocol that
is v2.0 (ID 0x20000), not v3.0 (ID 0x30000).

Fixes: 006d89b8f49f ("drivers: scmi-msg: add SCMI Voltage Domain protocol")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-sam: implement PL310 SMC protocol

When Linux runs in normal world, it expects the PL310 to be initially
disabled, and then invokes SMCs to enable it.
Let CFG_PL310_SIP_PROTOCOL=y, and the L2 ca

plat-sam: implement PL310 SMC protocol

When Linux runs in normal world, it expects the PL310 to be initially
disabled, and then invokes SMCs to enable it.
Let CFG_PL310_SIP_PROTOCOL=y, and the L2 cache will be left untouched
until the OS enables it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: update core local flags in native_intr_handler

The AArch32 version of the native_intr_handler() macro has until now
called C function without updating the core local flags to indicate

core: arm32: update core local flags in native_intr_handler

The AArch32 version of the native_intr_handler() macro has until now
called C function without updating the core local flags to indicate that
the temporary stack is in use. This can lead to errors with
CFG_CORE_DEBUG_CHECK_STACKS=y so fix this by setting THREAD_CLF_TMP and
THREAD_CLF_FIQ or THREAD_CLF_IRQ as needed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values.

drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values. This change allows to better fit the sole consumer of this
API function that is the SCMI server implementation. SCMI specification
states that discrete clock rates list shall follow this order.

Update at91_cpu_opp clock driver to ensure it satisfy this constraint.
The SAM platforms that embed this driver (sama7g5) already satisfy this
constraints but only at its DTS level. This change ensures the driver
will always.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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ta: pkcs11: correct RSA keys extended attributes sanitation

Fix RSA key attributes function load_tee_rsa_key_attrs() that badly
checks that the 5 extended RSA attributes are found in the key object.

ta: pkcs11: correct RSA keys extended attributes sanitation

Fix RSA key attributes function load_tee_rsa_key_attrs() that badly
checks that the 5 extended RSA attributes are found in the key object.

Link: https://github.com/OP-TEE/optee_test/issues/721#issuecomment-2068055537
Link: https://github.com/OP-TEE/optee_test/issues/721#issuecomment-2072064963
Fixes: 0442c956edfb ("ta: pkcs11: Add support for RSA signing & verification")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

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plat-stm32mp1: fix use after free in PMIC driver

Fix PMIC regulator levels arrays handling that missed a pointer reset
after the buffer is freed. At runtime, pmic_list_voltages() handler
function us

plat-stm32mp1: fix use after free in PMIC driver

Fix PMIC regulator levels arrays handling that missed a pointer reset
after the buffer is freed. At runtime, pmic_list_voltages() handler
function uses that reference and is expected to allocate back the
buffer in case non-secure world requests voltage enumeration for the
related regulator.

Fixes: a7990eb02b82 ("plat-stm32mp1: set voltage list at pmic driver init")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: apply "-march" and "-mabi" options to assembler

Update platform-aflags-generic to include the -march option. Without
specifying -march, the assembler will enable the C extension by defa

core: riscv: apply "-march" and "-mabi" options to assembler

Update platform-aflags-generic to include the -march option. Without
specifying -march, the assembler will enable the C extension by default
and generate compressed instructions, even if CFG_RISCV_ISA_C=n.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, ena

core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, enable RVC and FPU extension for QEMU virt machine.

Note that the RISC-V FPU for OP-TEE will be introduced later.
Enable FPU to temporarily bypass incompatible soft/hard-fp
linker errors.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: add build with Mbed TLS and crypto extensions

Build for QEMUv8 with Mbed TLS as the core crypto library and
cryptographic extensions enabled. This would have caught the issue fixed
in commit 021

ci: add build with Mbed TLS and crypto extensions

Build for QEMUv8 with Mbed TLS as the core crypto library and
cryptographic extensions enabled. This would have caught the issue fixed
in commit 021fee0affe5 ("core: mbedtls: Fix build").

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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kernel/link.mk: fix missing build number in version string on first build

Fix an issue with the build number in the version string. While at it,
factor out the duplicated code into mk/macros.mk.

Be

kernel/link.mk: fix missing build number in version string on first build

Fix an issue with the build number in the version string. While at it,
factor out the duplicated code into mk/macros.mk.

Before:

$ rm -rf out/
$ make out/arm-plat-vexpress/core/version.o
UPD out/arm-plat-vexpress/core/.buildcount
GEN out/arm-plat-vexpress/core/version.o
cat: out/arm-plat-vexpress/core/.buildcount: No such file or directory

In addition to the error message, note the missing build number after the
hash sign:

$ strings out/arm-plat-vexpress/core/version.o | grep UTC
4.3.0-48-g9c97e7d52 (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) # Wed Aug 14 16:17:07 UTC 2024 arm

After:

$ rm -rf out/
$ make out/arm-plat-vexpress/core/version.o
UPD out/arm-plat-vexpress/core/.buildcount
GEN out/arm-plat-vexpress/core/version.o
$ strings out/arm-plat-vexpress/core/version.o | grep UTC
4.3.0-48-g9c97e7d52-dev (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) #1 Wed Aug 14 16:17:24 UTC 2024 arm

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mk/compile.mk: separate rule to produce preprocessed dts files

When compiling a .dts into a .dtb, there is a pre-preprocessing phase
where the C preprocessor is run on the .dts to produce a .pre.dts

mk/compile.mk: separate rule to produce preprocessed dts files

When compiling a .dts into a .dtb, there is a pre-preprocessing phase
where the C preprocessor is run on the .dts to produce a .pre.dts, then
the device tree compiler is called to generate the .dtb. The two phases
are currently bundled into a single makefile recipe, which is not ideal.

Extract the preprocessing commands into a separate recipe to address
this concern. This allows to do for example:

make PLATFORM=stm32mp1-157A_DK1 \
out/arm-plat-stm32mp1/core/arch/arm/dts/stm32mp157a-dk1.pre.dts

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mk/compile.mk: remove duplicate dtc flags

When a .dts is compiled into a .dtb, the flags: '-I dts -O dtb
-Wno-unit_address_vs_reg' are present several times on the command line.
It is visible when b

mk/compile.mk: remove duplicate dtc flags

When a .dts is compiled into a .dtb, the flags: '-I dts -O dtb
-Wno-unit_address_vs_reg' are present several times on the command line.
It is visible when building with "make ... V=1".

Fix this by not appending to DTC_FLAGS but instead use DTC_FLAGS as is
from the environment and add the specific flags once to the compile
command.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mk/compile.mk: print dtc command when V=1

The command that compiles a device tree source file (.dts) into a
binary (.dtb) should be displayed when verbose mode is enabled
(V=1), but it is not the ca

mk/compile.mk: print dtc command when V=1

The command that compiles a device tree source file (.dts) into a
binary (.dtb) should be displayed when verbose mode is enabled
(V=1), but it is not the case. Fix that by replacing the @ with $(q).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mbedtls: Fix build

The macro 'MBEDTLS_INTERNAL_VALIDATE_RET()' was removed in upstream commit
https://github.com/Mbed-TLS/mbedtls/commit/cc0fd47531ffeffb3185db77a17ee113

The macro was a no-op

core: mbedtls: Fix build

The macro 'MBEDTLS_INTERNAL_VALIDATE_RET()' was removed in upstream commit
https://github.com/Mbed-TLS/mbedtls/commit/cc0fd47531ffeffb3185db77a17ee113

The macro was a no-op, so just remove the checks.

This fixes building OP-TEE with:

make PLATFORM=vexpress \
PLATFORM_FLAVOR=juno \
CFG_CRYPTOLIB_NAME=mbedtls \
CFG_CRYPTOLIB_DIR=lib/libmbedtls
...
lib/libmbedtls/core/hash.c: In function 'mbedtls_internal_sha1_process':
lib/libmbedtls/core/hash.c:205:9: error: implicit declaration of function 'MBEDTLS_INTERNAL_VALIDATE_RET'

Signed-off-by: Jacob Kroon <jacobkr@axis.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: boot_clear_memtag(): use core_mmu_for_each_map()

Use core_mmu_for_each_map() in boot_clear_memtag() to iterate over each
memory region and clear memory tags for each matching region.

Pre

core: arm: boot_clear_memtag(): use core_mmu_for_each_map()

Use core_mmu_for_each_map() in boot_clear_memtag() to iterate over each
memory region and clear memory tags for each matching region.

Preparing for future changes where more than one memory region may use
the same memory type.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mm: add core_mmu_for_each_map()

Add core_mmu_for_each_map() to iterate over all memory regions, struct
tee_mmap_region.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: mm: add core_mmu_for_each_map()

Add core_mmu_for_each_map() to iterate over all memory regions, struct
tee_mmap_region.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Zeroize unused parameters before thread_return_to_udomain()

Zeroize unused parameters before calling thread_return_to_udomain() to
avoid leaking information to the untrusted domain unin

core: riscv: Zeroize unused parameters before thread_return_to_udomain()

Zeroize unused parameters before calling thread_return_to_udomain() to
avoid leaking information to the untrusted domain unintentionally.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: increase size of abort stack to 4096

To avoid stack overruns with CFG_WITH_PAGER=y and
CFG_CORE_DEBUG_CHECK_STACKS=y increase the abort stack from 3072 to
4096.

Signed-off-by: Jens Wik

core: arm64: increase size of abort stack to 4096

To avoid stack overruns with CFG_WITH_PAGER=y and
CFG_CORE_DEBUG_CHECK_STACKS=y increase the abort stack from 3072 to
4096.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: hisilicon: add authenc algorithm

Add authenc algorithm for hisilicon SEC driver

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add_phys_mem(): fix mergeable physical memory

The test in add_phys_mem() to see if two physical memory ranges can be
merged only checks for overlapping memory ranges, but consecutive ranges
ar

core: add_phys_mem(): fix mergeable physical memory

The test in add_phys_mem() to see if two physical memory ranges can be
merged only checks for overlapping memory ranges, but consecutive ranges
are not detected even if they can be merged. Fix this by also checking
if the byte after the lowest range matches the beginning of the next
range.

The resulting merged entry might be mergeable with the previous or next
entry, so add checks for that and merge if possible.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mm: introduce struct memory_map

Introduce struct memory_map to keep track of the array of struct
tee_mmap_region, covering number of used entries and number of allocated
entries.

core_mmap_is

core: mm: introduce struct memory_map

Introduce struct memory_map to keep track of the array of struct
tee_mmap_region, covering number of used entries and number of allocated
entries.

core_mmap_is_end_of_table() and MEM_AREA_END are now unused so remove
them.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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libutils: add array helpers

Add helper function() to insert and remove an element from an array. The
helper functions shifts the elements in the array as needed to make room
or fill a room of an ele

libutils: add array helpers

Add helper function() to insert and remove an element from an array. The
helper functions shifts the elements in the array as needed to make room
or fill a room of an element at a certain position.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: pm: sam: specify suspend/resume hint based on suspend level

The regulators that are used with the sama5d2 platforms can enter
different levels of low power mode. In order to be able to act

drivers: pm: sam: specify suspend/resume hint based on suspend level

The regulators that are used with the sama5d2 platforms can enter
different levels of low power mode. In order to be able to act
accordingly, pass this information through suspend/resume hint.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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kernel: pm: add suspend type hint

When entering suspend type, the suspend level is platform dependent and
can be set to various values depending on these platform. In order to
allow platforms settin

kernel: pm: add suspend type hint

When entering suspend type, the suspend level is platform dependent and
can be set to various values depending on these platform. In order to
allow platforms setting it in a generic way when entering suspend,
reserve some bits in the suspend/resume hint to pass this information.
Driver can then used it in a platform independent way to execute
specific code depending on it.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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