core: imx: add support for i.MX95 EVK

Add the support for i.MX95 EVK

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: add i.MX95 SoC ID

add i.MX95 SoC ID

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: add i.MX95 registers

Add i.MX95 registers

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

ci: upgrade actions/cache@v3 to v4

Upgrade the "cache" action to address the CI warning:

"""
The following actions uses Node.js version which is deprecated and
will be forced to run on node20: acti

ci: upgrade actions/cache@v3 to v4

Upgrade the "cache" action to address the CI warning:

"""
The following actions uses Node.js version which is deprecated and
will be forced to run on node20: actions/cache@v3. For more info: [1]
"""

Link: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/ [1]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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mk/compile.mk: remove absolute build time paths

Some generated files get a __FILE_ID__ which include absolute
build time paths. Remove the paths and use plain file name.
Fixes yocto QA check.

Probl

mk/compile.mk: remove absolute build time paths

Some generated files get a __FILE_ID__ which include absolute
build time paths. Remove the paths and use plain file name.
Fixes yocto QA check.

Problem/bug:

$ strings ../image/lib/firmware/tee.elf | grep mikko
__FILE_ID__
_home_mikko_build_core_ta_pub_key_c
__FILE_ID__
_home_mikko_build_core_ldelf_hex_c
__FILE_ID__
_home_mikko_build_core_early_ta_fd02c9da_306c_48c7_a49c_bbd827ae86ee_c

With this patch:

$ strings ../image/lib/firmware/tee.elf | grep mikko
$ strings ../image/lib/firmware/tee.elf | grep FILE_ID | egrep \
"core_ta_pub_key_c|core_ldelf_hex_c|core_early_ta_fd02c9da_306c_4"
__FILE_ID__ core_ta_pub_key_c
__FILE_ID__ core_ldelf_hex_c
__FILE_ID__ core_early_ta_fd02c9da_306c_48c7_a49c_bbd827ae86ee_c

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Mikko Rapeli <mikko.rapeli@linaro.org>

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core: kernel: Fix checking register convention r1/x1 value of transfer_list

According to recently firmware handsoff spec [1]'s
"Register usage at handoff boundary", Transfer List's signature value
w

core: kernel: Fix checking register convention r1/x1 value of transfer_list

According to recently firmware handsoff spec [1]'s
"Register usage at handoff boundary", Transfer List's signature value
was changed from 0x40_b10b (3 bytes) to 4a0f_b10b (4 bytes).

As updating of TL's signature, register value of x1/r1 should be:

In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b->masked value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).

Therefore, it requires to separate mask and shift value for register
convention version field when checking each r1/x1 value.

This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.

2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.

This patch is a breaking change. It works only TF-A is updated.

Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]
Fixes: 508e2476b232 ("core: update transfer list header and signature")
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: sama5d2: update NVMEM cells

According to the customer Fuse Matrix of sama5d2, the cell length
is 32 bytes.

Fixes: 6c6c4d9eb45d ("dts: sama5d2: add NVMEM die_id node")
Fixes: 8bd542fcb2ae ("dts

dts: sama5d2: update NVMEM cells

According to the customer Fuse Matrix of sama5d2, the cell length
is 32 bytes.

Fixes: 6c6c4d9eb45d ("dts: sama5d2: add NVMEM die_id node")
Fixes: 8bd542fcb2ae ("dts: sama5d2: add huk node for the NVMEM hardware unique key")
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: nvmem: nvmem-huk: fix cell size and memory allocation issues

No longer free the HUK cell after at the end of the
"tee_otp_get_hw_unique_key" execution, because for the regression
test 4013,

drivers: nvmem: nvmem-huk: fix cell size and memory allocation issues

No longer free the HUK cell after at the end of the
"tee_otp_get_hw_unique_key" execution, because for the regression
test 4013, the "tee_otp_get_hw_unique_key" callback isn't
re-called then an invalid huk_cell pointer is used, leading the
following issue:

E/TC:0 0 Core data-abort at address 0x0 (translation fault)
E/TC:0 0 fsr 0x00000005 ttbr0 0x20087859 ttbr1 0x20080059 cidr 0x2
E/TC:0 0 cpu #0 cpsr 0x60000133
E/TC:0 0 r0 0x2007d8e8 r4 0x2007d8e8 r8 0x00102010 r12 0xfffc2a40
E/TC:0 0 r1 0x20089528 r5 0x2008954c r9 0x00000010 sp 0x20089508
E/TC:0 0 r2 0x20059164 r6 0x20060188 r10 0x00000020 lr 0x2000bcb3
E/TC:0 0 r3 0x00000000 r7 0x2008954c r11 0x20089684 pc 0x2000baa2
E/TC:0 0 TEE load address @ 0x20000000
E/TC:0 0 Call stack:
E/TC:0 0 0x2000baa2 nvmem_cell_malloc_and_read at core/drivers/nvmem/nvmem.c:62
E/TC:0 0 0x2000bcb3 tee_otp_get_hw_unique_key at core/drivers/nvmem/nvmem_huk.c:23
E/TC:0 0 0x20010e9f __huk_subkey_derive at core/kernel/huk_subkey.c:78
E/TC:0 0 0x200178c9 system_derive_ta_unique_key at core/pta/system.c:122
E/TC:0 0 0x2001382b pseudo_ta_enter_invoke_cmd at core/kernel/pseudo_ta.c:209
E/TC:0 0 0x20010d95 tee_ta_invoke_command at core/kernel/tee_ta_manager.c:765
E/TC:0 0 0x20019567 syscall_invoke_ta_command at core/tee/tee_svc.c:871
E/TC:0 0 0x20002178 scall_do_call at core/arch/arm/kernel/arch_scall_a32.S:54
E/TC:0 0 Panic 'unhandled pageable abort' at core/arch/arm/kernel/abort.c:582 <abort_handler>
E/TC:0 0 TEE load address @ 0x20000000
E/TC:0 0 Call stack:
E/TC:0 0 0x200039b1 print_kernel_stack at core/arch/arm/kernel/unwind_arm32.c:109
E/TC:0 0 0x2000ff05 __do_panic at core/kernel/panic.c:80
E/TC:0 0 0x20002f01 get_fault_type at core/arch/arm/kernel/abort.c:498
E/TC:0 0 0x2000077c thread_excp_vect at core/arch/arm/kernel/thread_a32.S:758

Moreover, the length of the HW unique key must be 16 bytes.
But the size of NVMEM cells can be larger than 16 bytes, for
example on samad5 the SFC is using 32 bytes cells. These changes
also allow the use of a NVMEM cell larger to the HW unique key
length, using the first 16 bytes of a cell.

Finally, the instance of the NVMEM cell data will be allocated once,
in the probe. Before, a new instance was allocated at each call
to tee_otp_get_hw_unique_key().

Fixes: fc7169686724 ("drivers: nvmem: add nvmem-huk driver")
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: nvmem: nvmem-die-id: fix cell length

Obviously, the cell length wasn't set during nvmem-die-id
driver probe and the subkey length was always used.

Signed-off-by: Thomas Perrot <thomas.perr

drivers: nvmem: nvmem-die-id: fix cell length

Obviously, the cell length wasn't set during nvmem-die-id
driver probe and the subkey length was always used.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: nvmem: atmel_sfc: check the length before read cell

Check requested NVMEM cells length in Atmel SFC driver to
prevent issues in case the length is greater than the fuse
size.

Signed-off-by

drivers: nvmem: atmel_sfc: check the length before read cell

Check requested NVMEM cells length in Atmel SFC driver to
prevent issues in case the length is greater than the fuse
size.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Translate to PA when allocating PGT with MMU enabled

If MMU is enabled, core_mmu_pgt_alloc() returns virtual address of PGT
instead of physical address. Thus, it leads to some errors wh

core: riscv: Translate to PA when allocating PGT with MMU enabled

If MMU is enabled, core_mmu_pgt_alloc() returns virtual address of PGT
instead of physical address. Thus, it leads to some errors when we
invoke pa_to_ppn() with returned PGT which is actually the virtual
address of that PGT.

Fix it by checking whether MMU is enabled or not. If MMU is enabled, we
translate the returned PGT to its physical address.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: lib: fix undefined behavior shift_out_of_bounds in libtomcrypt

Replace 'i64' with 'u64' data type for variables
requiring bitwise shift operations.

xtest error log - 4007_ed25519:
---
$ xtest

core: lib: fix undefined behavior shift_out_of_bounds in libtomcrypt

Replace 'i64' with 'u64' data type for variables
requiring bitwise shift operations.

xtest error log - 4007_ed25519:
---
$ xtest 4007_ed25519

E/TC:? 0 Undefined behavior shift_out_of_bounds at core/lib/libtomcrypt/src/pk/ec25519/tweetnacl.c:55 col 12
E/TC:0 0 Panic at core/kernel/ubsan.c:193 <__ubsan_handle_shift_out_of_bounds>
E/TC:0 0 TEE load address @ 0x8e100000
E/TC:0 0 Call stack:
E/TC:0 0 0x8e10d6c0 print_kernel_stack at optee_os/core/arch/arm/kernel/unwind_arm64.c:89
E/TC:0 0 0x8e130c7c __do_panic at optee_os/core/kernel/panic.c:73
E/TC:0 0 0x8e134c9c __ubsan_handle_shift_out_of_bounds at optee_os/core/kernel/ubsan.c:193
E/TC:0 0 0x8e1cc740 car25519 at optee_os/core/lib/libtomcrypt/src/pk/ec25519/tweetnacl.c:55 (discriminator 1)
E/TC:0 0 0x8e1cccbc M at optee_os/core/lib/libtomcrypt/src/pk/ec25519/tweetnacl.c:135
E/TC:0 0 0x8e1cced8 add at optee_os/core/lib/libtomcrypt/src/pk/ec25519/tweetnacl.c:261
E/TC:0 0 0x8e1ce594 scalarmult at optee_os/core/lib/libtomcrypt/src/pk/ec25519/tweetnacl.c:294
E/TC:0 0 0x8e1ce6ac scalarbase at optee_os/core/lib/libtomcrypt/src/pk/ec25519/tweetnacl.c:307
E/TC:0 0 0x8e1cf184 tweetnacl_crypto_sk_to_pk at optee_os/core/lib/libtomcrypt/src/pk/ec25519/tweetnacl.c:317
E/TC:0 0 0x8e1c063c ed25519_make_key at optee_os/core/lib/libtomcrypt/src/pk/ed25519/ed25519_make_key.c:25 (discriminator 2)
E/TC:0 0 0x8e1bfef8 crypto_acipher_gen_ed25519_key at optee_os/core/lib/libtomcrypt/ed25519.c:64
E/TC:0 0 0x8e16b228 tee_svc_obj_generate_key_ed25519 at optee_os/core/tee/tee_svc_cryp.c:2312
E/TC:0 0 0x8e108110 scall_do_call at optee_os/core/arch/arm/kernel/arch_scall_a64.S:140
E/TC:0 0 0x8e107544 thread_scall_handler at optee_os/core/arch/arm/kernel/thread.c:1138
E/TC:0 0 0x8e1048b4 el0_svc at optee_os/core/arch/arm/kernel/thread_a64.S:850
---

Signed-off-by: Abhishek Revadekar <abhishek.rvdkr@yahoo.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix undefined behavior nonnull_args in user_access.c

Add null pointer checks on 'kaddr' and 'uaddr' before memcpy
to avoid ubsan 'nonnull_args' panic.

xtest error log - 4013
---
$ xtest 4013

core: fix undefined behavior nonnull_args in user_access.c

Add null pointer checks on 'kaddr' and 'uaddr' before memcpy
to avoid ubsan 'nonnull_args' panic.

xtest error log - 4013
---
$ xtest 4013

E/TC:? 0 Undefined behavior nonnull_arg at core/kernel/user_access.c:56 col 3
E/TC:1 0 Panic at core/kernel/ubsan.c:241 <__ubsan_handle_nonnull_arg>
E/TC:1 0 TEE load address @ 0x8e100000
E/TC:1 0 Call stack:
E/TC:1 0 0x8e10d6c0 print_kernel_stack at optee_os/core/arch/arm/kernel/unwind_arm64.c:89
E/TC:1 0 0x8e130c7c __do_panic at optee_os/core/kernel/panic.c:73
E/TC:1 0 0x8e134eac __ubsan_handle_nonnull_arg at optee_os/core/kernel/ubsan.c:241
E/TC:1 0 0x8e135a48 copy_from_user at optee_os/core/kernel/user_access.c:56
E/TC:1 0 0x8e157198 system_derive_ta_unique_key at optee_os/core/pta/system.c:111
E/TC:1 0 0x8e141258 pseudo_ta_enter_invoke_cmd at optee_os/core/kernel/pseudo_ta.c:209
E/TC:1 0 0x8e13401c tee_ta_invoke_command at optee_os/core/kernel/tee_ta_manager.c:765
E/TC:1 0 0x8e162dac syscall_invoke_ta_command at optee_os/core/tee/tee_svc.c:871
E/TC:1 0 0x8e108110 scall_do_call at optee_os/core/arch/arm/kernel/arch_scall_a64.S:140
E/TC:1 0 0x8e107544 thread_scall_handler at optee_os/core/arch/arm/kernel/thread.c:1138
E/TC:1 0 0x8e1048b4 el0_svc at optee_os/core/arch/arm/kernel/thread_a64.S:850
---

Signed-off-by: Abhishek Revadekar <abhishek.rvdkr@yahoo.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: kernel: print node name on provider driver registering failure

Print the name of the node when failing to register a provider driver
in DT_DRIVER framework.

Signed-off-by: Etienne Carriere <e

core: kernel: print node name on provider driver registering failure

Print the name of the node when failing to register a provider driver
in DT_DRIVER framework.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

core: kernel: dt_driver: fix nodes reference passed in dt_pargs

Correct the DT node references passed in struct dt_pargs. Field
phandle_node is expected to be the node offset of the provider driver

core: kernel: dt_driver: fix nodes reference passed in dt_pargs

Correct the DT node references passed in struct dt_pargs. Field
phandle_node is expected to be the node offset of the provider driver
but dt_driver_device_from_node_idx_prop_phandle() implementation passes
node offset -1, dt_driver_device_from_parent() passes the consumer
node offset and dt_driver_device_from_node_idx_prop() may pass the
phandle node offset from a previous index in the parsed DT node property.

Fix that by adding field consumer_node to reference the node offset of
the consumer device and fixing phandle_node where applicable and
update atmel_i2c and stm32_i2c drivers to get the I2C device address
from the consumer_node field instead of the phandle_node that is now
fixed.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

show more ...

drivers: crypto: hisilicon: fix incorrect use of error code

Fix incorrect use of memory-related error code in hash algorithm.

Fixes: 94c8a3397ec4 ("drivers: crypto: hisilicon:Add HASH and HMAC algo

drivers: crypto: hisilicon: fix incorrect use of error code

Fix incorrect use of memory-related error code in hash algorithm.

Fixes: 94c8a3397ec4 ("drivers: crypto: hisilicon:Add HASH and HMAC algorithm")
Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: crypto: hisilicon: Add cipher algorithm

Add DES, 3DES, AES and SM4 cipher algorithm

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by

drivers: crypto: hisilicon: Add cipher algorithm

Add DES, 3DES, AES and SM4 cipher algorithm

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm32: force CFG_LPAE_ADDR_SPACE_BITS=32

AArch32/Arm7 can only use 32 bits for virtual addresses so force that
configuration to avoid inconsistencies.

Signed-off-by: Jens Wiklander <jens.wikl

core: arm32: force CFG_LPAE_ADDR_SPACE_BITS=32

AArch32/Arm7 can only use 32 bits for virtual addresses so force that
configuration to avoid inconsistencies.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: mmu_v7: remove non-working ns-virtualization

Removes the nonworking CFG_NS_VIRTUALIZATION code from core_mmu_v7.c.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: arm: mmu_v7: remove non-working ns-virtualization

Removes the nonworking CFG_NS_VIRTUALIZATION code from core_mmu_v7.c.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: mobj_phys_alloc(): remove unused memory types

In mobj_phys_alloc() remove support for the two unused memory types
CORE_MEM_TEE_RAM and CORE_MEM_TA_RAM.

Signed-off-by: Jens Wiklander <jens.wik

core: mobj_phys_alloc(): remove unused memory types

In mobj_phys_alloc() remove support for the two unused memory types
CORE_MEM_TEE_RAM and CORE_MEM_TA_RAM.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: remove unused mobj_sec_ddr

Remove the unused global variable mobj_sec_ddr.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.co

core: remove unused mobj_sec_ddr

Remove the unused global variable mobj_sec_ddr.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: arm: mm: remove unused map_memarea_sections()

Remove the unused function map_memarea_sections().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etien

core: arm: mm: remove unused map_memarea_sections()

Remove the unused function map_memarea_sections().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: arm: increase tmp stack for CFG_NS_VIRTUALIZATION

CFG_NS_VIRTUALIZATION requires slightly more stack when enabled so add
that to the group of conditions using the larger tmp stack.

Signed-off

core: arm: increase tmp stack for CFG_NS_VIRTUALIZATION

CFG_NS_VIRTUALIZATION requires slightly more stack when enabled so add
that to the group of conditions using the larger tmp stack.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: leverage qsort_int() in PMIC driver

Use recently added qsort_int() helper function.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.w

plat-stm32mp1: leverage qsort_int() in PMIC driver

Use recently added qsort_int() helper function.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutils: qsort helper for standard types

Add qsort_int(), qsort_uint(), qsort_u32() and friends as qsort() helper
functions to sort standard typed arrays.

Signed-off-by: Etienne Carriere <etienne.

libutils: qsort helper for standard types

Add qsort_int(), qsort_uint(), qsort_u32() and friends as qsort() helper
functions to sort standard typed arrays.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...