core: stack check: fix debug message

The lower limit for thread stacks printed by print_stack_limits()
when CFG_CORE_DEBUG_CHECK_STACKS=y is incorrect. It needs to be
increased by STACK_CHECK_EXTRA

core: stack check: fix debug message

The lower limit for thread stacks printed by print_stack_limits()
when CFG_CORE_DEBUG_CHECK_STACKS=y is incorrect. It needs to be
increased by STACK_CHECK_EXTRA to be consistent with the value
returned by get_stack_soft_limits(). While we're at it, improve
the SP out of range message to make it EMSG() rather than DMSG() and
show the stack limits. This makes it easier to identify in which
stack the pointer was supposed to be.

Here is an example of a stack overflow panic in thread 0:

D/TC:? 0 ldelf_syscall_open_bin:142 Lookup user TA ELF cb3e5ba0-adf1-11e0-998b-0002a5d5c51b (Secure Storage TA)
E/TC:? 0 Stack pointer out of range! 0x7e7bd618 not in [0x7e7bd630 .. 0x7e7bf030]
D/TC:? 0 print_stack_limits:179 tmp [0] 0x7e7c1c90..0x7e7c24b0
D/TC:? 0 print_stack_limits:179 tmp [1] 0x7e7c2ad0..0x7e7c32f0
D/TC:? 0 print_stack_limits:179 tmp [2] 0x7e7c3910..0x7e7c4130
D/TC:? 0 print_stack_limits:179 tmp [3] 0x7e7c4750..0x7e7c4f70
D/TC:? 0 print_stack_limits:184 abt [0] 0x7e7b8710..0x7e7b9330
D/TC:? 0 print_stack_limits:184 abt [1] 0x7e7b9950..0x7e7ba570
D/TC:? 0 print_stack_limits:184 abt [2] 0x7e7bab90..0x7e7bb7b0
D/TC:? 0 print_stack_limits:184 abt [3] 0x7e7bbdd0..0x7e7bc9f0
D/TC:? 0 print_stack_limits:189 thr [0] 0x7e7bd630..0x7e7bf030
D/TC:? 0 print_stack_limits:189 thr [1] 0x7e7bfc70..0x7e7c1670
E/TC:1 0 Panic at core/kernel/thread.c:207 <check_stack_limits>
E/TC:1 0 TEE load address @ 0x7e6e5000
E/TC:1 0 Call stack:
E/TC:1 0 0x7e6f1b10 print_kernel_stack at optee_os/core/arch/arm/kernel/unwind_arm64.c:80
E/TC:1 0 0x7e7071b8 __do_panic at optee_os/core/kernel/panic.c:24
E/TC:1 0 0x7e70cd14 check_stack_limits at optee_os/core/kernel/thread.c:207
E/TC:1 0 0x7e70dcd8 __cyg_profile_func_enter at optee_os/core/kernel/thread.c:237
E/TC:1 0 0x7e766b74 memset at optee_os/lib/libutils/isoc/newlib/memset.c:76
E/TC:1 0 0x7e768928 memzero_explicit at optee_os/lib/libutils/ext/memzero_explicit.c:22
E/TC:1 0 0x7e74de54 zeromem at optee_os/core/lib/libtomcrypt/src/misc/zeromem.c:26 (discriminator 2)
E/TC:1 0 0x7e74ddd8 burn_stack at optee_os/core/lib/libtomcrypt/src/misc/burn_stack.c:24
E/TC:1 0 0x7e74a32c rijndael_ecb_encrypt at optee_os/core/lib/libtomcrypt/src/ciphers/aes/aes.c:454
E/TC:1 0 0x7e743e44 crypto_aes_enc_block at optee_os/core/lib/libtomcrypt/aes.c:45 (discriminator 2)
E/TC:1 0 0x7e6fa1d0 decrypt_block at optee_os/core/crypto/aes-gcm-sw.c:98
E/TC:1 0 0x7e6fa2ec decrypt_pl at optee_os/core/crypto/aes-gcm-sw.c:118 (discriminator 3)
E/TC:1 0 0x7e6fa400 internal_aes_gcm_update_payload_blocks at optee_os/core/crypto/aes-gcm-sw.c:143
E/TC:1 0 0x7e6f93f4 __gcm_update_payload at optee_os/core/crypto/aes-gcm.c:246
E/TC:1 0 0x7e6f9504 operation_final at optee_os/core/crypto/aes-gcm.c:273
E/TC:1 0 0x7e6f9780 __gcm_dec_final at optee_os/core/crypto/aes-gcm.c:328
E/TC:1 0 0x7e6f9840 internal_aes_gcm_dec_final at optee_os/core/crypto/aes-gcm.c:342
E/TC:1 0 0x7e6f9a64 aes_gcm_dec_final at optee_os/core/crypto/aes-gcm.c:500
E/TC:1 0 0x7e6f85cc crypto_authenc_dec_final at optee_os/core/crypto/crypto.c:427
E/TC:1 0 0x7e7352d8 authenc_decrypt_final at optee_os/core/tee/fs_htree.c:511
E/TC:1 0 0x7e736094 tee_fs_htree_read_block at optee_os/core/tee/fs_htree.c:899
E/TC:1 0 0x7e732234 ree_fs_read_primitive at optee_os/core/tee/tee_ree_fs.c:340
E/TC:1 0 0x7e7334e8 read_dent at optee_os/core/tee/fs_dirfile.c:103
E/TC:1 0 0x7e734024 tee_fs_dirfile_open at optee_os/core/tee/fs_dirfile.c:143
E/TC:1 0 0x7e731ab4 open_dirh at optee_os/core/tee/tee_ree_fs.c:552
E/TC:1 0 0x7e731b50 get_dirh at optee_os/core/tee/tee_ree_fs.c:573
E/TC:1 0 0x7e732e38 ree_fs_open at optee_os/core/tee/tee_ree_fs.c:626
E/TC:1 0 0x7e72ec60 tadb_open at optee_os/core/tee/tadb.c:227
E/TC:1 0 0x7e72f3a0 tee_tadb_open at optee_os/core/tee/tadb.c:246 (discriminator 1)
E/TC:1 0 0x7e72ff7c tee_tadb_ta_open at optee_os/core/tee/tadb.c:643
E/TC:1 0 0x7e70fed8 secstor_ta_open at optee_os/core/kernel/secstor_ta.c:19
E/TC:1 0 0x7e706648 ldelf_syscall_open_bin at optee_os/core/kernel/ldelf_syscalls.c:145
E/TC:1 0 0x7e6f54c0 tee_svc_do_call at optee_os/core/arch/arm/tee/arch_svc_a64.S:140
E/TC:1 0 0x7e6ec780 thread_svc_handler at optee_os/core/arch/arm/kernel/thread.c:1104 (discriminator 4)
E/TC:1 0 0x7e6ea35c el0_svc at optee_os/core/arch/arm/kernel/thread_a64.S:825

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix handling of CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA

CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA should be included in
STACK_THREAD_SIZE and STACK_TMP_SIZE, respectively, because

core: fix handling of CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA

CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA should be included in
STACK_THREAD_SIZE and STACK_TMP_SIZE, respectively, because not doing so
creates inconsistencies where some places use e.g., (STACK_THREAD_SIZE +
CFG_STACK_THREAD_EXTRA) while others use STACK_THREAD_SIZE only. Note
for example the discrepancy between the stack declaration:

DECLARE_STACK(stack_thread, CFG_NUM_THREADS,
STACK_THREAD_SIZE + CFG_STACK_THREAD_EXTRA, static);

...and the thread_stack_start() function:

vaddr_t thread_stack_start(void)
{
/* ... */

return thr->stack_va_end - STACK_THREAD_SIZE;
}

With this change, the _EXTRA values should also be properly taken into
account when pager is enabled, which was not the case before.

Fixes: cca7b5ebeb9b ("core: configuration switches to tune stack sizes")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge@foundries.io> (STM32MP1, SE050, pager)

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core: add allocator for cache aligned memory

Provides new common maximum cache line aligned allocator for allocating
memory to be used when communicating with different peripherals within the
CPU.

core: add allocator for cache aligned memory

Provides new common maximum cache line aligned allocator for allocating
memory to be used when communicating with different peripherals within the
CPU.

Allocated memory can be readily used with cache maintenance operations.

This is based on core/drivers/imx/dcp/dcp_utils.c.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sort includes in tee_misc.c

Sort includes to keep it clean.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: dt_driver: rework dt_driver_register_provider()

Registering a provider shouldn't fail when a provider node has no
phandle. It only means that no node refer to the provider device hence
the pro

core: dt_driver: rework dt_driver_register_provider()

Registering a provider shouldn't fail when a provider node has no
phandle. It only means that no node refer to the provider device hence
the provider reference does not need to be registered.

This change protects from issues when, for example, device-tree compiler
removes unused phandle to optimize DTB image size.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver: Add support for disabled devices

In systems where there are multiple instances of the devices like two TRNGs
where one is reserved for REE environment and one is for TEE environment

core: dt_driver: Add support for disabled devices

In systems where there are multiple instances of the devices like two TRNGs
where one is reserved for REE environment and one is for TEE environment
those can be defined in device tree in following way:

ree-trng {
status = "okay";
secure-status = "disabled";
...
}

tee-trng {
status = "disabled";
secure-status = "okay";
...
}

If OP-TEE has driver enabled for the device both devices will be probed.

Driver can detect device's 'status' and 'secure-status' settings and return
TEE_ERROR_NODE_DISABLED value for one that is not for its use.

This will indicate to device driver probing to continue without an error.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add support to parse TPM eventlog and extend PCRs

Support for OP-TEE to parse the TPM eventlog. The eventlog format
is based on TCG specification [1], so we call this TCG framework.

To parse

core: Add support to parse TPM eventlog and extend PCRs

Support for OP-TEE to parse the TPM eventlog. The eventlog format
is based on TCG specification [1], so we call this TCG framework.

To parse the eventlog and extend PCR's device is needed which
supports PCR's. This device can be TPM or any other HSM which
supports PCR like registers. Such a device can register itself
as a TCG provider for PCR information and ability to extend the
PCR's.

[1] TCG PC Client Platform Firmware Profile Specification
link: https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification/

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: syscalls: strip tags from user space pointers

Strips the tags from user space pointers before using them.
We're relying on TCR_EL1.TCMA0=1 to make the accesses unchecked.

Acked-by: Jerome For

core: syscalls: strip tags from user space pointers

Strips the tags from user space pointers before using them.
We're relying on TCR_EL1.TCMA0=1 to make the accesses unchecked.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add support for MTE

Adds support for the Armv8.5-A Memory Tagging Extension with
CFG_MEMTAG=y.

A memtag.h API is introduced to handle this extension. If CFG_MEMTAG=n
the API doesn't add any o

core: add support for MTE

Adds support for the Armv8.5-A Memory Tagging Extension with
CFG_MEMTAG=y.

A memtag.h API is introduced to handle this extension. If CFG_MEMTAG=n
the API doesn't add any overhead and the behaviour is unchanged. With
CFG_MEMTAG=y a check is performed to see if the platform can support MTE
and the API is dynamically configured accordingly. This means that it's
safe to have CFG_MEMTAG=y even for platforms not supporting MTE. There
will be some minimal overhead then, but likely not noticeable.

An entry is also added in the TEE_PROPSET_TEE_IMPLEMENTATION for a u32
property "org.trustedfirmware.optee.cpu.feat_memtag_implemented". The
property is set to a non-zero value only if CFG_CORE_MEMTAG is
configured and the underlying CPU supports FEAT_MTE.

This commit still only uses the default tag with the value 0 resulting
in unchanged pointers when accessing memory. However, all plumbing is in
place allowing for instance tagging of the heap in a later commit.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: map TA memory using TEE_MATTR_MEM_TYPE_TAGGED

Maps TA memory using the TEE_MATTR_MEM_TYPE_TAGGED which results in
tagged cached memory if the system has it enabled.

Acked-by: Etienne Carriere

core: map TA memory using TEE_MATTR_MEM_TYPE_TAGGED

Maps TA memory using the TEE_MATTR_MEM_TYPE_TAGGED which results in
tagged cached memory if the system has it enabled.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt_driver: allow parsing of phandle == 0

In Linux, it is allowed to specify a null phandle which means it should
be skipped. Add support for this specific case by simply skipping over
it. This

core: dt_driver: allow parsing of phandle == 0

In Linux, it is allowed to specify a null phandle which means it should
be skipped. Add support for this specific case by simply skipping over
it. This is needed to parse assigned-clock-parents which can use such
syntax. This is specified in the clock bindings [1] which says the
following:

To skip setting parent or rate of a clock its corresponding entry
should be set to 0, or can be omitted if it is not followed by any
non-zero entry

For example this is a valid device-tree description:

assigned-clocks = <foo>, <bar>;
assigned-clock-parents = <0> <bar_parent>;
assigned-clock-rates = <1000>;

Link: [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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core: fix use after free in tee_ta_open_session()

Fixes a use after free where the session pointer 's' was used after
tee_ta_close_session() while recovering from an error.

Fixes: 82061b8d7b34 ("co

core: fix use after free in tee_ta_open_session()

Fixes a use after free where the session pointer 's' was used after
tee_ta_close_session() while recovering from an error.

Fixes: 82061b8d7b34 ("core: store TA params in session struct")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: FF-A: Map TPM event log for FF-A SPs

Enable passing the TPM event log to FF-A SPs if their manifest has an
"arm,tpm_event_log" compatible node. The event log is mapped to the
SP's address spac

core: FF-A: Map TPM event log for FF-A SPs

Enable passing the TPM event log to FF-A SPs if their manifest has an
"arm,tpm_event_log" compatible node. The event log is mapped to the
SP's address space and the address and size fields are updated in the
SP manifest.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Imre Kis <imre.kis@arm.com>

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core: Enable mapping DT from secure memory

Add CFG_MAP_EXT_DT_SECURE option to enable mapping the device tree from
the secure memory. As the device tree in the secure memory would only
have the even

core: Enable mapping DT from secure memory

Add CFG_MAP_EXT_DT_SECURE option to enable mapping the device tree from
the secure memory. As the device tree in the secure memory would only
have the event log address in the secure memory the property name is
changed from tpm_event_log_sm_addr to the standard tpm_event_log_addr
when CFG_MAP_EXT_DT_SECURE is enabled.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Imre Kis <imre.kis@arm.com>

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core: dt_driver: drivers to test probe deferral

Implements driver providers for some emulated resource (clocks and reset
controllers), consumer drivers and a embedded test DTSI file to
test the DT_D

core: dt_driver: drivers to test probe deferral

Implements driver providers for some emulated resource (clocks and reset
controllers), consumer drivers and a embedded test DTSI file to
test the DT_DRIVER probe sequence.

The driver consumer run few tests and logs results locally. The
result participates in core self test result reported by the
PTA test interface.

One can test with vexpress platform flavor qemu_virt and qemu_v8 using,
for example, the build instruction below:
make PLATFORM=vexpress-qemu_virt \
CFG_DT_DRIVER_EMBEDDED_TEST=y \
CFG_EMBED_DTB_SOURCE_FILE=embedded_dtb_test.dts

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt: add kernel DT API to retrieved device information from DT

Add _fdt_read_uint32_array(), _fdt_read_uint32(),
_fdt_read_uint32_default(), _fdt_check_node() functions.

Acked-by: Etienne Carr

core: dt: add kernel DT API to retrieved device information from DT

Add _fdt_read_uint32_array(), _fdt_read_uint32(),
_fdt_read_uint32_default(), _fdt_check_node() functions.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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core: tag ops structures with __relrodata_unpaged

Global structures currently tagged with __rodata_unpaged need to use
__relrodata_unpaged instead because they contain pointers which are
subject to

core: tag ops structures with __relrodata_unpaged

Global structures currently tagged with __rodata_unpaged need to use
__relrodata_unpaged instead because they contain pointers which are
subject to relocation when CFG_CORE_ASLR=y. Doing so moves them out of
.rodata which will now stay unmodified even with ASLR turned on.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: suppress text relocation on stack_tmp_export

stack_tmp_export is a pointer so it is associated with a dynamic
relocation when position-independent code is generated (ASLR). Moreover,
this symb

core: suppress text relocation on stack_tmp_export

stack_tmp_export is a pointer so it is associated with a dynamic
relocation when position-independent code is generated (ASLR). Moreover,
this symbol is in the .identity_map section, which is part of .text after
the final link. To get rid of this TEXTREL, remove stack_tmp_export and
compute the corresponding value in assembly instead from stack_tmp and
constants defined in core/arch/arm/kernel/asm-defines.c.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move NOTIF_VALUE_DO_BOTTOM_HALF assert to thread_optee_smc.c

Moves the compile assertion that NOTIF_VALUE_DO_BOTTOM_HALF matches
OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF in core/kernel/notif

core: move NOTIF_VALUE_DO_BOTTOM_HALF assert to thread_optee_smc.c

Moves the compile assertion that NOTIF_VALUE_DO_BOTTOM_HALF matches
OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF in core/kernel/notif.c to
core/arch/arm/kernel/thread_optee_smc.c to keep dependencies to
optee_smc.h in architecture specific code.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: tee_ta_manager.c: remove arm.h from includes

Header file arm.h is not used in tee_ta_manager.c, remove it from includes
such that can reuse it with new architecture.

Signed-off-by: Ma

core: kernel: tee_ta_manager.c: remove arm.h from includes

Header file arm.h is not used in tee_ta_manager.c, remove it from includes
such that can reuse it with new architecture.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move thread_defs.h into thread.h

Moves the defines in core/arch/arm/include/kernel/thread_defs.h into
core/include/kernel/thread.h.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-

core: move thread_defs.h into thread.h

Moves the defines in core/arch/arm/include/kernel/thread_defs.h into
core/include/kernel/thread.h.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split core/arch/arm/kernel/thread.c

Splits core/arch/arm/kernel/thread.c into one generic and one
architecture specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marou

core: split core/arch/arm/kernel/thread.c

Splits core/arch/arm/kernel/thread.c into one generic and one
architecture specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: move spin_lock_debug.c to core/kernel

Source file spin_lock_debug.c does not contain architecture-specific code
therefore, move it from core/arch/arm/kernel to core/kernel and remove
u

core: kernel: move spin_lock_debug.c to core/kernel

Source file spin_lock_debug.c does not contain architecture-specific code
therefore, move it from core/arch/arm/kernel to core/kernel and remove
unused header thread_private.h

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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Add basic pointer authentication support for TA's

APIAKey is used for usespace TA's where these keys are generated
for every TA at load time. The TEE core maintains the key value
for each TA is resp

Add basic pointer authentication support for TA's

APIAKey is used for usespace TA's where these keys are generated
for every TA at load time. The TEE core maintains the key value
for each TA is responsible for storing/restorign them during
switch to EL0 and back.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: add reset controller framework

Adds a common reset controller framework rstctrl for interfacing
reset controllers exposed by a platform.

Reset controller consumers can act on relate reset

drivers: add reset controller framework

Adds a common reset controller framework rstctrl for interfacing
reset controllers exposed by a platform.

Reset controller consumers can act on relate reset level with
rstctrl_assert(), rstctrl_deassert() and friends.

Reset controller consumers can claim exclusive access to the reset
level woth rstctrl_get_exclusive(), rstctrl_put_exclusive().

Reset controller provider drivers call rstctrl_register_provider()
to allow other drivers to get a reset control reference from
a devicetree reference. Reset controller driver are identified with
type DT_DRIVER_RSTCTRL.

A reset controller provider exposes struct rstctrl instances made of
an opaque private reference (a private data pointer or an unsigned
integer identifier), an reset controller operators reference and
the exclusive claim state.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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