1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32_iwdg.h> 13 #include <drivers/stm32_tamp.h> 14 #include <drivers/stm32_uart.h> 15 #include <drivers/stm32mp1_etzpc.h> 16 #include <dt-bindings/clock/stm32mp1-clks.h> 17 #include <kernel/boot.h> 18 #include <kernel/dt.h> 19 #include <kernel/interrupt.h> 20 #include <kernel/misc.h> 21 #include <kernel/panic.h> 22 #include <kernel/spinlock.h> 23 #include <mm/core_memprot.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stm32_util.h> 27 #include <trace.h> 28 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 36 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB4_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 42 43 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 44 45 #define _ID2STR(id) (#id) 46 #define ID2STR(id) _ID2STR(id) 47 48 static TEE_Result platform_banner(void) 49 { 50 #ifdef CFG_EMBED_DTB 51 IMSG("Platform stm32mp1: flavor %s - DT %s", 52 ID2STR(PLATFORM_FLAVOR), 53 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 54 #else 55 IMSG("Platform stm32mp1: flavor %s - no device tree", 56 ID2STR(PLATFORM_FLAVOR)); 57 #endif 58 59 return TEE_SUCCESS; 60 } 61 service_init(platform_banner); 62 63 /* 64 * Console 65 * 66 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 67 * trace console. Value 0 disables the early console. 68 * 69 * We cannot use the generic serial_console support since probing 70 * the console requires the platform clock driver to be already 71 * up and ready which is done only once service_init are completed. 72 */ 73 static struct stm32_uart_pdata console_data; 74 75 void console_init(void) 76 { 77 /* Early console initialization before MMU setup */ 78 struct uart { 79 paddr_t pa; 80 bool secure; 81 } uarts[] = { 82 [0] = { .pa = 0 }, 83 [1] = { .pa = USART1_BASE, .secure = true, }, 84 [2] = { .pa = USART2_BASE, .secure = false, }, 85 [3] = { .pa = USART3_BASE, .secure = false, }, 86 [4] = { .pa = UART4_BASE, .secure = false, }, 87 [5] = { .pa = UART5_BASE, .secure = false, }, 88 [6] = { .pa = USART6_BASE, .secure = false, }, 89 [7] = { .pa = UART7_BASE, .secure = false, }, 90 [8] = { .pa = UART8_BASE, .secure = false, }, 91 }; 92 93 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 94 95 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 96 return; 97 98 /* No clock yet bound to the UART console */ 99 console_data.clock = NULL; 100 101 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 102 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 103 104 register_serial_console(&console_data.chip); 105 106 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 107 } 108 109 #ifdef CFG_EMBED_DTB 110 static TEE_Result init_console_from_dt(void) 111 { 112 struct stm32_uart_pdata *pd = NULL; 113 void *fdt = NULL; 114 int node = 0; 115 TEE_Result res = TEE_ERROR_GENERIC; 116 117 fdt = get_embedded_dt(); 118 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 119 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 120 fdt = get_external_dt(); 121 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 122 if (res == TEE_ERROR_ITEM_NOT_FOUND) 123 return TEE_SUCCESS; 124 if (res != TEE_SUCCESS) 125 return res; 126 } 127 128 pd = stm32_uart_init_from_dt_node(fdt, node); 129 if (!pd) { 130 IMSG("DTB disables console"); 131 register_serial_console(NULL); 132 return TEE_SUCCESS; 133 } 134 135 /* Replace early console with the new one */ 136 console_flush(); 137 console_data = *pd; 138 free(pd); 139 register_serial_console(&console_data.chip); 140 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 141 142 return TEE_SUCCESS; 143 } 144 145 /* Probe console from DT once clock inits (service init level) are completed */ 146 service_init_late(init_console_from_dt); 147 #endif 148 149 /* 150 * GIC init, used also for primary/secondary boot core wake completion 151 */ 152 static struct gic_data gic_data; 153 154 void itr_core_handler(void) 155 { 156 gic_it_handle(&gic_data); 157 } 158 159 void main_init_gic(void) 160 { 161 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 162 itr_init(&gic_data.chip); 163 164 stm32mp_register_online_cpu(); 165 } 166 167 void main_secondary_init_gic(void) 168 { 169 gic_cpu_init(&gic_data); 170 171 stm32mp_register_online_cpu(); 172 } 173 174 static TEE_Result init_stm32mp1_drivers(void) 175 { 176 /* Without secure DTB support, some drivers must be inited */ 177 if (!IS_ENABLED(CFG_EMBED_DTB)) 178 stm32_etzpc_init(ETZPC_BASE); 179 180 /* Secure internal memories for the platform, once ETZPC is ready */ 181 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 182 etzpc_lock_tzma(0); 183 184 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 185 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 186 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 187 188 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 189 etzpc_lock_tzma(1); 190 191 return TEE_SUCCESS; 192 } 193 194 service_init_late(init_stm32mp1_drivers); 195 196 static TEE_Result init_late_stm32mp1_drivers(void) 197 { 198 TEE_Result res = TEE_ERROR_GENERIC; 199 200 /* Set access permission to TAM backup registers */ 201 if (IS_ENABLED(CFG_STM32_TAMP)) { 202 struct stm32_bkpregs_conf conf = { 203 .nb_zone1_regs = TAMP_BKP_REGISTER_ZONE1_COUNT, 204 .nb_zone2_regs = TAMP_BKP_REGISTER_ZONE2_COUNT, 205 }; 206 207 res = stm32_tamp_set_secure_bkpregs(&conf); 208 if (res == TEE_ERROR_DEFER_DRIVER_INIT) { 209 /* TAMP driver was not probed if disabled in the DT */ 210 res = TEE_SUCCESS; 211 } 212 if (res) 213 panic(); 214 } 215 216 return TEE_SUCCESS; 217 } 218 219 driver_init_late(init_late_stm32mp1_drivers); 220 221 vaddr_t stm32_rcc_base(void) 222 { 223 static struct io_pa_va base = { .pa = RCC_BASE }; 224 225 return io_pa_or_va_secure(&base, 1); 226 } 227 228 vaddr_t get_gicd_base(void) 229 { 230 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 231 232 return io_pa_or_va_secure(&base, 1); 233 } 234 235 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 236 { 237 cfg->base = BSEC_BASE; 238 cfg->upper_start = STM32MP1_UPPER_OTP_START; 239 cfg->max_id = STM32MP1_OTP_MAX_ID; 240 } 241 242 bool stm32mp_is_closed_device(void) 243 { 244 uint32_t otp = 0; 245 TEE_Result result = TEE_ERROR_GENERIC; 246 247 /* Non closed_device platform expects fuse well programmed to 0 */ 248 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 249 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 250 return false; 251 252 return true; 253 } 254 255 bool __weak stm32mp_with_pmic(void) 256 { 257 return false; 258 } 259 260 uint32_t may_spin_lock(unsigned int *lock) 261 { 262 if (!lock || !cpu_mmu_enabled()) 263 return 0; 264 265 return cpu_spin_lock_xsave(lock); 266 } 267 268 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 269 { 270 if (!lock || !cpu_mmu_enabled()) 271 return; 272 273 cpu_spin_unlock_xrestore(lock, exceptions); 274 } 275 276 static vaddr_t stm32_tamp_base(void) 277 { 278 static struct io_pa_va base = { .pa = TAMP_BASE }; 279 280 return io_pa_or_va_secure(&base, 1); 281 } 282 283 static vaddr_t bkpreg_base(void) 284 { 285 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 286 } 287 288 vaddr_t stm32mp_bkpreg(unsigned int idx) 289 { 290 return bkpreg_base() + (idx * sizeof(uint32_t)); 291 } 292 293 #ifdef CFG_STM32_GPIO 294 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 295 { 296 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 297 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 298 299 /* Get secure mapping address for GPIOZ */ 300 if (bank == GPIO_BANK_Z) 301 return io_pa_or_va_secure(&gpioz_base, GPIO_BANK_OFFSET); 302 303 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 304 assert(bank <= GPIO_BANK_K); 305 306 return io_pa_or_va_nsec(&gpios_nsec_base, 307 (bank + 1) * GPIO_BANK_OFFSET) + 308 (bank * GPIO_BANK_OFFSET); 309 } 310 311 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 312 { 313 if (bank == GPIO_BANK_Z) 314 return 0; 315 316 assert(bank <= GPIO_BANK_K); 317 return bank * GPIO_BANK_OFFSET; 318 } 319 320 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 321 { 322 if (bank == GPIO_BANK_Z) 323 return GPIOZ; 324 325 assert(bank <= GPIO_BANK_K); 326 return GPIOA + bank; 327 } 328 329 #ifdef CFG_DRIVERS_CLK 330 struct clk *stm32_get_gpio_bank_clk(unsigned int bank) 331 { 332 if (bank == GPIO_BANK_Z) 333 return stm32mp_rcc_clock_id_to_clk(GPIOZ); 334 335 assert(bank <= GPIO_BANK_K); 336 return stm32mp_rcc_clock_id_to_clk(GPIOA + bank); 337 } 338 #endif 339 #endif /* CFG_STM32_GPIO */ 340 341 #ifdef CFG_STM32_IWDG 342 TEE_Result stm32_get_iwdg_otp_config(paddr_t pbase, 343 struct stm32_iwdg_otp_data *otp_data) 344 { 345 unsigned int idx = 0; 346 uint32_t otp_value = 0; 347 348 switch (pbase) { 349 case IWDG1_BASE: 350 idx = 0; 351 break; 352 case IWDG2_BASE: 353 idx = 1; 354 break; 355 default: 356 panic(); 357 } 358 359 if (stm32_bsec_read_otp(&otp_value, HW2_OTP)) 360 panic(); 361 362 otp_data->hw_enabled = otp_value & 363 BIT(idx + HW2_OTP_IWDG_HW_ENABLE_SHIFT); 364 otp_data->disable_on_stop = otp_value & 365 BIT(idx + HW2_OTP_IWDG_FZ_STOP_SHIFT); 366 otp_data->disable_on_standby = otp_value & 367 BIT(idx + HW2_OTP_IWDG_FZ_STANDBY_SHIFT); 368 369 return TEE_SUCCESS; 370 } 371 #endif /*CFG_STM32_IWDG*/ 372