| #
76d6685e |
| 17-Dec-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
tree-wide: use power-of-2 rounding macros where applicable
Use ROUNDUP2(), ROUNDUP2_OVERFLOW(), ROUNDUP2_DIV() and ROUNDDOWN2() at places where the rounding argument is a variable value and we want
tree-wide: use power-of-2 rounding macros where applicable
Use ROUNDUP2(), ROUNDUP2_OVERFLOW(), ROUNDUP2_DIV() and ROUNDDOWN2() at places where the rounding argument is a variable value and we want to leverage the implementation of these routines optimized for a power-of-2 rounding argument.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
5ca2c365 |
| 10-Jan-2024 |
Clement Faure <clement.faure@nxp.com> |
core: remove unnecessary includes
Remove unnecessary includes.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander
core: remove unnecessary includes
Remove unnecessary includes.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
33e931b1 |
| 23-Dec-2022 |
Mark-PK Tsai <mark-pk.tsai@mediatek.com> |
core: Correct the description of core_is_buffer_outside
Correct the function description of core_is_buffer_outside in comment.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com> Reviewed-by: J
core: Correct the description of core_is_buffer_outside
Correct the function description of core_is_buffer_outside in comment.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
4682bf0f |
| 30-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
core: add allocator for cache aligned memory
Provides new common maximum cache line aligned allocator for allocating memory to be used when communicating with different peripherals within the CPU.
core: add allocator for cache aligned memory
Provides new common maximum cache line aligned allocator for allocating memory to be used when communicating with different peripherals within the CPU.
Allocated memory can be readily used with cache maintenance operations.
This is based on core/drivers/imx/dcp/dcp_utils.c.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
f6b4561a |
| 29-Jul-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
core: sort includes in tee_misc.c
Sort includes to keep it clean.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
c3682b1c |
| 15-May-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: make core_is_buffer_*() paddr_t compatible
The core_is_buffer_*() helpers are sometimes used with physical addresses (type paddr_t). This can cause problem on platforms where sizeof(paddr_t) >
core: make core_is_buffer_*() paddr_t compatible
The core_is_buffer_*() helpers are sometimes used with physical addresses (type paddr_t). This can cause problem on platforms where sizeof(paddr_t) > sizeof(vaddr_t), that is on ARM32 systems with CFG_CORE_LARGE_PHYS_ADDR=y. The FVP platform compiled for AArch32 is one such system which as a consequence fails with: E/TC:0 0 check_phys_mem_is_outside:335 Non-sec mem (0x880000000:0x180000000) ove rlaps map (type 12 0xff000000:0x1000000) E/TC:0 0 Panic at core/arch/arm/mm/core_mmu.c:336 <check_phys_mem_is_outside>
This patch fixes this problem by taking input addresses as paddr_t and sizes as paddr_ssize_t instead. The wrapper macros which did some automatic casting removed. The requires updates at some of the places where these functions are called.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
385000b0 |
| 01-Oct-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: correct overflows in range overlap functions
Buffers that end at end of the available address range which may happen on 32bit machine fail have an end address that of computed as 0. This chang
core: correct overflows in range overlap functions
Buffers that end at end of the available address range which may happen on 32bit machine fail have an end address that of computed as 0. This change uses the computation already used in _core_is_buffer_inside() to ensure functions _core_is_buffer_outside() and _core_is_buffer_intersect() return a reliable result.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
dc0f4ec2 |
| 16-May-2018 |
Etienne Carriere <etienne.carriere@st.com> |
Remove license notice from STMicroelectronics files
Since a while the source files license info are defined by SPDX identifiers. We can safely remove the verbose license text from the files that are
Remove license notice from STMicroelectronics files
Since a while the source files license info are defined by SPDX identifiers. We can safely remove the verbose license text from the files that are owned by either only STMicroelectronics or only both Linaro and STMicroelectronics.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
1bb92983 |
| 15-Dec-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
Add SPDX license identifiers
Adds one SPDX-License-Identifier line [1] to each source files that contains license text.
Generated by [2]: spdxify.py --add-spdx optee_os/
The scancode tool [3] wa
Add SPDX license identifiers
Adds one SPDX-License-Identifier line [1] to each source files that contains license text.
Generated by [2]: spdxify.py --add-spdx optee_os/
The scancode tool [3] was used to double check the license matching code in the Python script. All the licenses detected by scancode are either detected by spdxify.py, or have no SPDX identifier, or are false matches.
Link: [1] https://spdx.org/licenses/ Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py Link: [3] https://github.com/nexB/scancode-toolkit Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org>
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| #
fe3ccf24 |
| 30-Nov-2015 |
Jerome Forissier <jerome.forissier@linaro.org> |
libutils: add %pUl format for UUIDs
The debug traces in tee_ta_manager.c do not show the last 8 bytes of the TA UUIDs, which makes the output confusing sometimes. This commit adds support for a new
libutils: add %pUl format for UUIDs
The debug traces in tee_ta_manager.c do not show the last 8 bytes of the TA UUIDs, which makes the output confusing sometimes. This commit adds support for a new printf format for little-endian encoded UUIDs: %pUl, and uses it in tee_ta_manager.c. For example:
TEE_UUID uuid; DMSG("UUID: %pUl", (void *)&uuid);
...will print something like:
[...] UUID: cb3e5ba0-adf1-11e0-998b0002a5d5c51b
The new format is available when using the trace macros or the new functions: snprintk(), vsnprintk() declared in <printk.h>. But, snprintf() and vsnprintf() are not modified in order not to break standard compliance.
This format is taken from the Linux kernel [1].
[1] https://www.kernel.org/doc/Documentation/printk-formats.txt
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
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| #
d87d5ede |
| 15-Jun-2015 |
Peng Fan <van.freenix@gmail.com> |
core: mm: fix adding integer overflow issue
On ARMv7 platform, it is easy that "base + size" wraps down to 0. For example, base is 0xfc100000, size is 0x3f00000, then base + size is 0. We should use
core: mm: fix adding integer overflow issue
On ARMv7 platform, it is easy that "base + size" wraps down to 0. For example, base is 0xfc100000, size is 0x3f00000, then base + size is 0. We should use the "end" address to do the comparation, but not "end + 1".
This patch also can be used for ARMv8.
Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (QEMU platform) Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey 32/64-bit)
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| #
5580c17c |
| 03-Dec-2014 |
Etienne Carriere <etienne.carriere@st.com> |
core/arm32: add traces in case of user TA abort
TA manager and TA mmu layer have specific trace handlers for TA aborts: - dumping TA info. - dumping TA mapping info.
Generic helper uuid2str().
Sig
core/arm32: add traces in case of user TA abort
TA manager and TA mmu layer have specific trace handlers for TA aborts: - dumping TA info. - dumping TA mapping info.
Generic helper uuid2str().
Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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| #
4de4bebc |
| 20-Oct-2014 |
Jens Wiklander <jens.wiklander@linaro.org> |
Merge tee_{core,uta}_trace.h into libutil
Merges tee_core_trace.h and tee_uta_trace.h into a common trace.h in libutil. Since the trace functions now resides libutil they have to rely on core and li
Merge tee_{core,uta}_trace.h into libutil
Merges tee_core_trace.h and tee_uta_trace.h into a common trace.h in libutil. Since the trace functions now resides libutil they have to rely on core and libutee to provide functions to print to the log device.
* Keeps compatible interface from tee_kta_trace.h * Adds TAMSG() and TAMSG_RAW() to log TA related events * Removes the TRACE_ALWAYS level
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt platform) Reviewed-by: Etienne Carriere <etienne.carriere@st.com> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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| #
37d6ae92 |
| 28-Oct-2014 |
Pascal Brand <pascal.brand@st.com> |
core_tlb_maintenance(TLBINV_BY_ASID) is on
It also contains code style cleanup
Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by:
core_tlb_maintenance(TLBINV_BY_ASID) is on
It also contains code style cleanup
Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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| #
106d8aa6 |
| 23-Oct-2014 |
Pascal Brand <pascal.brand@st.com> |
core: generic buffer inside/outside/intersect routine
Remove multiple implementation of "is buffer inside a buffer" and friends and rely on a generic core_is_buffer_inside/outside/intersect().
Revi
core: generic buffer inside/outside/intersect routine
Remove multiple implementation of "is buffer inside a buffer" and friends and rely on a generic core_is_buffer_inside/outside/intersect().
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Signed-off-by: Pascal Brand <pascal.brand@st.com>
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| #
54e04708 |
| 23-Oct-2014 |
Pascal Brand <pascal.brand@st.com> |
Move tee_misc in generic part
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
|