| bdde1c99 | 18-Mar-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_i2c: protect bus access with a mutex
Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by:
drivers: stm32_i2c: protect bus access with a mutex
Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c80790fe | 12-Mar-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: use mutex_pm_aware
Use newly introduced struct mutex_pm_aware semaphore to protect regulator accesses.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Eti
drivers: regulator: use mutex_pm_aware
Use newly introduced struct mutex_pm_aware semaphore to protect regulator accesses.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 9a3248fc | 29-Feb-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: replace clock main spinlock with a mutex
Change clock framework lock from an interrupts masked spinning lock to a mutex. This allows the clock framework to better handle slow stabilizi
drivers: clk: replace clock main spinlock with a mutex
Change clock framework lock from an interrupts masked spinning lock to a mutex. This allows the clock framework to better handle slow stabilizing clocks as PLLs without masking the system interrupt which can have side effects on the REE or even the TEE.
To support clock accesses during low power state transition sequences while non-secure world is no operating, the lock is not taken when the execution is not in the scope of a TEE thread.
This change is not expected to impact supported platforms that currently only access clock operation from thread contexts or atomic PM sequences.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 3a20c661 | 12-Mar-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: kernel: mutex compliant with PM sequences
Add mutex_pm_aware_*() functions for mutex used on resources accessed at runtime using a conventional mutex and also during low power sequences that e
core: kernel: mutex compliant with PM sequences
Add mutex_pm_aware_*() functions for mutex used on resources accessed at runtime using a conventional mutex and also during low power sequences that execute in a non-thread context.
This change defines MUTEX_PM_AWARE_INITIALIZER macro from a new header file (mutex_pm_aware.h) instead of existing mutex.h to prevent a circular dependency between spinlock.h (requires thread.h), thread.h (indirectly includes mutex.h) and mutex.h (that would depend on spinlock.h for definition of the SPINLOCK_UNLOCK macro ).
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| f6412fbd | 12-Mar-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: kernel: thread spin locking
Add thread_spin_lock() and thread_spin_unlock() for active spinning locks in situation where we need an exclusive lock in a thread and interruptible context even at
core: kernel: thread spin locking
Add thread_spin_lock() and thread_spin_unlock() for active spinning locks in situation where we need an exclusive lock in a thread and interruptible context even at the cost of a high CPU usage.
These function are intended to be used in thread context hence they assert being executed in such a context. This is to prevent on mistakenly spin in an atomic context which potentially leads to a deadlock situation.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 1cf7e98d | 14-Mar-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: replace REGISTER_TIME_SOURCE()
Remove REGISTER_TIME_SOURCE() and implement tee_time_get_sys_time() and tee_time_get_sys_time_protection_level() directly in the file where REGISTER_TIME_SOURCE(
core: replace REGISTER_TIME_SOURCE()
Remove REGISTER_TIME_SOURCE() and implement tee_time_get_sys_time() and tee_time_get_sys_time_protection_level() directly in the file where REGISTER_TIME_SOURCE() was used previously.
By avoiding indirect calls the linker can optimize the dependency tree properly and we can remove the DECLARE_KEEP_PAGER() directive needed for arm_cntpct_time_source.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| b2f99d20 | 01-Feb-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
core: boot: fix memtag init sequence
Based on following observations on FVP: With boot_init_memtag called before MMU enable, DC GZA hits an alignment fault. This is because all accesses are of devic
core: boot: fix memtag init sequence
Based on following observations on FVP: With boot_init_memtag called before MMU enable, DC GZA hits an alignment fault. This is because all accesses are of device type when MMU is off. Arm ARM states for DC GZA: "If the memory region being modified is any type of Device memory, this instruction can give an alignment fault." Moving boot_init_memtag after MMU enable, DC GZA hits a permission fault, this is because the range returned by core_mmu_get_secure_memory consists of pages mapped RO (text sections) and then RW (data sections) consecutively. DC GZA is a write instruction executed towards an RO page leading to a fault.
To fix this, split boot_init_memtag into two halves: - Setup memtag operations before MMU is enabled such that MAIR_EL1 is properly configured for normal tagged memory. - Clear core TEE RW sections after MMU is enabled.
Closes: https://github.com/OP-TEE/optee_os/issues/6649 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> [jw rewrote boot_clear_memtag()] Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c41db53b | 01-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: define generic callout service initializer
Add a generic timer_init_callout_service() to be implemented in architecture or platform specific code. The function shall provide an implementation
core: define generic callout service initializer
Add a generic timer_init_callout_service() to be implemented in architecture or platform specific code. The function shall provide an implementation of the abstract timer interface needed by the callout service and register a timer interrupt callback to call callout_service_cb().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| cf707bd0 | 31-Jan-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add callout service
Add a callout service to call registered callback functions at a given time from now. A callout is periodic or oneshot depending on how the callback function returns. Callb
core: add callout service
Add a callout service to call registered callback functions at a given time from now. A callout is periodic or oneshot depending on how the callback function returns. Callback functions execute in nexus and interrupt context.
The callout service is initialized with callout_service_init() and depends on an abstract timer interface to manage the hardware timer. callout_service_cb() needs to be called from the timer interrupt handler to drive the callout service.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b4d1c08a | 30-Jan-2024 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
drivers: regulator: do not cache voltage level value
Always read current voltage level from the device instead of caching the level in struct regulator. This fixes issues for when the regulator leve
drivers: regulator: do not cache voltage level value
Always read current voltage level from the device instead of caching the level in struct regulator. This fixes issues for when the regulator level value depends on the parent regulator (supply). It is up the regulator drivers to cache or not this value in their private data if applicable.
Fixes: 1a3d3273040b ("drivers: regulator framework") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c4cdfb70 | 06-Mar-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add __must_check attribute to cpu_spin_lock_xsave()
cpu_spin_lock_xsave() masks exceptions, takes the spinlock and returns previous exception state to be restored by cpu_spin_unlock_xrestore()
core: add __must_check attribute to cpu_spin_lock_xsave()
cpu_spin_lock_xsave() masks exceptions, takes the spinlock and returns previous exception state to be restored by cpu_spin_unlock_xrestore(). The previously returned exception state must always be supplied so add the __must_check attribute to cpu_spin_lock_xsave() and its debug variants.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| ccd64a52 | 02-Mar-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: kernel: add timeout_elapsed_us()
Add API function timeout_elapsed_us() to measure to time since or until an initialized timeout reference elapses.
This function relies on other timeout_*() AP
core: kernel: add timeout_elapsed_us()
Add API function timeout_elapsed_us() to measure to time since or until an initialized timeout reference elapses.
This function relies on other timeout_*() API functions are therefore depends on CFG_CORE_HAS_GENERIC_TIMER being enabled.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| fab37ad7 | 02-Mar-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: kernel: factorize delay and timeout implementation
Factorize RISC-V and Arm architectures implementation of delay and timeout API functions into generic core kernel source directory.
Architec
core: kernel: factorize delay and timeout implementation
Factorize RISC-V and Arm architectures implementation of delay and timeout API functions into generic core kernel source directory.
Architecture or platform only need to implement timer tick count read function delay_cnt_read() and timer tick frequency (in Hertz) delay_cnt_freq() which is related to CFG_CORE_HAS_GENERIC_TIMER support.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 6b0ac81d | 12-Jul-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: kernel: describe udelay()/mdelay()
Add inline description comment for udelay() and mdelay() for consistency of OP-TEE OS source tree, even if the function names are quite explicit and do not s
core: kernel: describe udelay()/mdelay()
Add inline description comment for udelay() and mdelay() for consistency of OP-TEE OS source tree, even if the function names are quite explicit and do not strictly need such descriptions.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 943d822a | 12-Sep-2023 |
Tony Han <tony.han@microchip.com> |
drivers: clk: sam: add sama7g5 clock description
Define PLL, master, system, peripheral, generic clocks for sama7g5 and register the clocks to clock provider.
Signed-off-by: Tony Han <tony.han@micr
drivers: clk: sam: add sama7g5 clock description
Define PLL, master, system, peripheral, generic clocks for sama7g5 and register the clocks to clock provider.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 458ef442 | 21-Feb-2024 |
Alvin Chang <alvinga@andestech.com> |
drivers: Implement semihosting based console driver for log
Implement a simple console driver which uses semihosting operations to read/write the trace messages. There are two paths to output the tr
drivers: Implement semihosting based console driver for log
Implement a simple console driver which uses semihosting operations to read/write the trace messages. There are two paths to output the trace messages: - If the caller of semihosting_console_init() provides the path of the file, the driver will try to open that file, and output the log to that host side file. - If the caller of semihosting_console_init() does not provide the path of the file, the driver will connect the console to the host debug console directly.
If CFG_SEMIHOSTING_CONSOLE is enabled, OP-TEE will try to initialize the semihosting console driver by given CFG_SEMIHOSTING_CONSOLE_FILE.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 55ab8f06 | 27-Feb-2024 |
Alvin Chang <alvinga@andestech.com> |
core: Refactor console_init() and introduce plat_console_init()
Since there are some cross-platform console drivers, we let console_init() be common code to have a chance to initialize those console
core: Refactor console_init() and introduce plat_console_init()
Since there are some cross-platform console drivers, we let console_init() be common code to have a chance to initialize those console drivers (e.g., semihosting console).
If the cross-platform console drivers are not configured to be compiled, plat_console_init() will be invoked to initialize platform-specific console driver.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7e2a1038 | 21-Feb-2024 |
Alvin Chang <alvinga@andestech.com> |
core: kernel: Add semihosting functions
Semihosting is a mechanism that enables target to communicate and use I/O facilities on a host computer which is running a debugger, such as GDB. The I/O faci
core: kernel: Add semihosting functions
Semihosting is a mechanism that enables target to communicate and use I/O facilities on a host computer which is running a debugger, such as GDB. The I/O facilities include character {read|write} {from|to} the semihosting host side console or a file. In other words, OP-TEE OS can output log to the host side console or the host side file, if there is a semihosting host and OP-TEE OS requests the semihosting operations to that host.
If CFG_SEMIHOSTING is enabled, some semihosting functions will be compiled into OP-TEE kernel, including: - semihosting_sys_readc() - semihosting_sys_writec() - semihosting_open() - semihosting_read() - semihosting_write() - semihosting_close()
Note that the architectures which support semihosting should provide their implementation of __do_semihosting(), which performs semihosting instruction to raise the semihosting request.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| eb3951bf | 10-Nov-2023 |
Thomas Perrot <thomas.perrot@bootlin.com> |
plat-sam: register additional sama7g5 clocks for SCMI usage
- Add the macro definitions for each SCMI clock. - Add the table of PMC-SCMI map for sama7g5 clocks.
Signed-off-by: Thomas Perrot <thomas
plat-sam: register additional sama7g5 clocks for SCMI usage
- Add the macro definitions for each SCMI clock. - Add the table of PMC-SCMI map for sama7g5 clocks.
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 609ba8e3 | 12-Sep-2023 |
Tony Han <tony.han@microchip.com> |
plat-sam: register sama7g5 clocks for SCMI usage
Add the macro definitions for each SCMI clock. Add the table of PMC-SCMI map for sama7g5 clocks.
Signed-off-by: Tony Han <tony.han@microchip.com> Ac
plat-sam: register sama7g5 clocks for SCMI usage
Add the macro definitions for each SCMI clock. Add the table of PMC-SCMI map for sama7g5 clocks.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| f8c1dacb | 22-Feb-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: make API function description more consistent
Change inline description comments of clock framework API functions, macros and structures to be more consistent.
Reviewed-by: Gatien Che
drivers: clk: make API function description more consistent
Change inline description comments of clock framework API functions, macros and structures to be more consistent.
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 8baaac1c | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: pre-enable new parent on clock re-parent
Add new clock flag CLK_SET_PARENT_PRE_ENABLE for when an already enabled clock is re-parented and the new parent clock must be enabled before w
drivers: clk: pre-enable new parent on clock re-parent
Add new clock flag CLK_SET_PARENT_PRE_ENABLE for when an already enabled clock is re-parented and the new parent clock must be enabled before we switch of parents.
This is needed for some system clocks that cannot be disabled, for example an interconnect AXI bus clock or a CPU clock.
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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| 8fbc0056 | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: get linear rates description
Implement clk_get_rates_steps() clock API function to get the supported clock rates description as a triplet min/max/step. This function can be used in the
drivers: clk: get linear rates description
Implement clk_get_rates_steps() clock API function to get the supported clock rates description as a triplet min/max/step. This function can be used in the scope of SCMI communication where a clock can report a linear rate list without listing all supported clock is an array which size could be quite big.
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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| 20f97d98 | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: enable clock on rate change
Add new clock flag CLK_SET_RATE_UNGATE for clocks that must be enabled in order to change their rate.
Reviewed-by: Gatien Chevallier <gatien.chevallier@fos
drivers: clk: enable clock on rate change
Add new clock flag CLK_SET_RATE_UNGATE for clocks that must be enabled in order to change their rate.
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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| 0ba7ae74 | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: change parent clock rate if needed
Add clock flag CLK_SET_RATE_PARENT for clocks for which rate change request must be propagated to the parent clock.
Reviewed-by: Gatien Chevallier <
drivers: clk: change parent clock rate if needed
Add clock flag CLK_SET_RATE_PARENT for clocks for which rate change request must be propagated to the parent clock.
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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