| c6738340 | 16-Oct-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: increases RSA prime retry
Change the RSA Primes generation retry loops: - Reduce number of loops set in the job ring descriptor. - Add software loop to not lock the system.
Total ret
drivers: caam: increases RSA prime retry
Change the RSA Primes generation retry loops: - Reduce number of loops set in the job ring descriptor. - Add software loop to not lock the system.
Total retry loop has been increased because RSA 4096 generation key test might fail sometimes.
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| 90072753 | 17-Feb-2021 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: remove unused SGT functions
Remove not longer used SGT functions.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 6997f698 | 08-Apr-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: use CAAM DMA object in math driver
Update the math driver to use the CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@lin
drivers: caam: use CAAM DMA object in math driver
Update the math driver to use the CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| a9591ed5 | 06-Apr-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: use CAAM DMA object in RSA
Update the RSA driver to use the CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> |
| eafbaf2c | 31-Mar-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: use CAAM DMA object in Cipher
Update Cipher driver to use the CAAM DMA object - Cipher AES/DES/DES3 all modes - Cipher MAC
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Sign
drivers: caam: use CAAM DMA object in Cipher
Update Cipher driver to use the CAAM DMA object - Cipher AES/DES/DES3 all modes - Cipher MAC
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 3dface8c | 27-Mar-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: use CAAM DMA object in HMAC
Update HMAC driver to use the CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Ac
drivers: caam: use CAAM DMA object in HMAC
Update HMAC driver to use the CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 865a5792 | 25-Mar-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: use CAAM DMA object in Hash
Update Hash driver to use the CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Ac
drivers: caam: use CAAM DMA object in Hash
Update Hash driver to use the CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 53d714df | 27-Mar-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: add dmaobj descriptor functions
Add descriptor operation to handle caamdmaobj to set: - SGT data type - Extension length
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Acked-by
drivers: caam: add dmaobj descriptor functions
Add descriptor operation to handle caamdmaobj to set: - SGT data type - Extension length
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 38923d48 | 27-Mar-2020 |
Cedric Neveux <cedric.neveux@nxp.com> |
drivers: caam: implement CAAM DMA Object
Implementation of a CAAM DMA object to: - create a DMA object (SGT/buffer) based on input/output buffers - reallocate a new buffer accessible from the CA
drivers: caam: implement CAAM DMA Object
Implementation of a CAAM DMA object to: - create a DMA object (SGT/buffer) based on input/output buffers - reallocate a new buffer accessible from the CAAM address space - ensure buffer is cache aligned (for the output)
Implementation of CAAM DMA object functions to: - cache maintenance - free CAAM DMA object
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| e0e51e3f | 05-Mar-2021 |
Franck LENORMAND <franck.lenormand@nxp.com> |
drivers: caam: fix read of length of D component
Read the RSA D component with caam_read_val32() which handles endianness. The CAAM endianness might differ between IMX and LS platforms.
Signed-off-
drivers: caam: fix read of length of D component
Read the RSA D component with caam_read_val32() which handles endianness. The CAAM endianness might differ between IMX and LS platforms.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 659a1f88 | 09-Mar-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: rename agent_id to channel_id
Rename agent_id reference to channel_id to avoid confusion with the agent identifiers used in SCMI protocol to identify agent, whereas the drivers on
drivers: scmi-msg: rename agent_id to channel_id
Rename agent_id reference to channel_id to avoid confusion with the agent identifiers used in SCMI protocol to identify agent, whereas the drivers only reference an SCMI channel, whatever the agent ID associated with the channel and knowing that an SCMI agent can have several channels to communicate with the SCMI platform/server.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome@forissier.org>
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| de266e27 | 23-Feb-2021 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: imx_rngb: random number generator
Add support for the RNG(B) as described in the i.MX 6ULL Applications Processor Reference Manual, Rev 1, 11/2017.
Tested on an imx6ull based board.
Signe
drivers: imx_rngb: random number generator
Add support for the RNG(B) as described in the i.MX 6ULL Applications Processor Reference Manual, Rev 1, 11/2017.
Tested on an imx6ull based board.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 65b5ada4 | 02-Mar-2021 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: drivers: stm32_rng.c: include thread.h
The implementation makes use of thread_mask_exceptions() and thread_unmask_exceptions() functions, therefore, include thread.h to avoid compilation error
core: drivers: stm32_rng.c: include thread.h
The implementation makes use of thread_mask_exceptions() and thread_unmask_exceptions() functions, therefore, include thread.h to avoid compilation errors.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8537f7eb | 02-Mar-2021 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: driver: stpmic1: do not use TEE_Result as return type
stpmic1_regulator_levels_mv() uses TEE_Result as return type. The caller on core/arch/arm/plat-stm32mp1/scmi_server.c does not check the r
core: driver: stpmic1: do not use TEE_Result as return type
stpmic1_regulator_levels_mv() uses TEE_Result as return type. The caller on core/arch/arm/plat-stm32mp1/scmi_server.c does not check the return value, therefore, change it to void.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 4a9ea08c | 08-Mar-2021 |
Fangsuo Wu <fangsuowu@asrmicro.com> |
drivers: gic: fix the off-by-one error
The gd->max_it should refer to the largest support interrupt id. Fix the off-by-one errors so that the interrupt with the largest id can be correctly handled.
drivers: gic: fix the off-by-one error
The gd->max_it should refer to the largest support interrupt id. Fix the off-by-one errors so that the interrupt with the largest id can be correctly handled.
Acked-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
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| 3513f269 | 03-Mar-2021 |
Manish Tomar <manish.tomar@nxp.com> |
plat-ls: Add DSPI driver for NXP LS Platforms
This patch adds DSPI driver for Layerscape Platforms. DSPI compilation is enabled by default for LX2160A-QDS and LX2160A-RDB.
Signed-off-by: Carl Lamb
plat-ls: Add DSPI driver for NXP LS Platforms
This patch adds DSPI driver for Layerscape Platforms. DSPI compilation is enabled by default for LX2160A-QDS and LX2160A-RDB.
Signed-off-by: Carl Lamb <calamb@microsoft.com> Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| 16c13b4d | 23-Feb-2021 |
Manish Tomar <manish.tomar@nxp.com> |
plat-ls: Add GPIO driver for NXP LS Platforms
This patch adds GPIO driver for Layerscape Platforms. GPIO compilation is enabled by default for LX2160A-QDS and LX2160A-RDB.
Signed-off-by: Manish Tom
plat-ls: Add GPIO driver for NXP LS Platforms
This patch adds GPIO driver for Layerscape Platforms. GPIO compilation is enabled by default for LX2160A-QDS and LX2160A-RDB.
Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Acked-by: Victor Chong <victor.chong@linaro.org> Reviewed-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
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| fc5d98e8 | 23-Feb-2021 |
Manish Tomar <manish.tomar@nxp.com> |
core: gpio.h: Add 'struct gpio_chip *chip' in 'struct gpio_ops'
To get the GPIO controller base address, 'struct gpio_chip *chip' is passed as a member in the container 'struct gpio_ops'
Also updat
core: gpio.h: Add 'struct gpio_chip *chip' in 'struct gpio_ops'
To get the GPIO controller base address, 'struct gpio_chip *chip' is passed as a member in the container 'struct gpio_ops'
Also updated bcm_gpio and pl061_gpio as per modified gpio.h definition.
Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Reviewed-by: Victor Chong <victor.chong@linaro.org> Reviewed-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
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| 6c2162fa | 12-Feb-2021 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: fix allocated buffer size
When a buffer is allocated for output CAAM operations, the output buffer cache is invalidated beforehand.
To avoid data loss, an allocated buffer size shoul
drivers: caam: fix allocated buffer size
When a buffer is allocated for output CAAM operations, the output buffer cache is invalidated beforehand.
To avoid data loss, an allocated buffer size should be a multiple data cacheline size.
Fixes: b22795b ("drivers: caam: make use of generic memalign() implementation") Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| a392e112 | 12-Feb-2021 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: use dcache_get_line_size()
Remove CAAM function to get the data cache line size and use the generic function.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jens W
drivers: caam: use dcache_get_line_size()
Remove CAAM function to get the data cache line size and use the generic function.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 819d0141 | 20-Nov-2020 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
plat-ls: add i2c driver for NXP LS Platforms
I2C Driver compilation is enabled by default for LX2160A-RDB and LX2160A-QDS.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Reviewed-by: Jens W
plat-ls: add i2c driver for NXP LS Platforms
I2C Driver compilation is enabled by default for LX2160A-RDB and LX2160A-QDS.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Clement Faure <clement.faure@nxp.com>
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| 41494d18 | 12-Feb-2021 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: se050: Foundries Plug-and-Trust Release 0.0.2
The Foundries Plug-and-Trust library tracks NXP Plug-and-Trust quaterly releases.
Modifications in the NXP library sources require a new prepro
crypto: se050: Foundries Plug-and-Trust Release 0.0.2
The Foundries Plug-and-Trust library tracks NXP Plug-and-Trust quaterly releases.
Modifications in the NXP library sources require a new preprocessor macro to be defined.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Jerome Forissier <jerome@forissier.org>
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| 530faff2 | 12-Feb-2021 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: crypto: se050: improve maintainability
Replace explicit c-flags duplication across makefiles with single shared definition.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed
drivers: crypto: se050: improve maintainability
Replace explicit c-flags duplication across makefiles with single shared definition.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Jerome Forissier <jerome@forissier.org>
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| b22795b7 | 22-Jan-2021 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: make use of generic memalign() implementation
Make use of the newly implemented memalign() function for the CAAM driver. Remove the previous CAAM memalign() implementation and its ass
drivers: caam: make use of generic memalign() implementation
Make use of the newly implemented memalign() function for the CAAM driver. Remove the previous CAAM memalign() implementation and its associated debugging structures.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 93e678ed | 24-Sep-2020 |
Clement Faure <clement.faure@nxp.com> |
drivers: dcp: add DCP support
The Data Co-Processor (DCP) provides hardware acceleraiton for cryptographic algorithms. The features of DCP are: - AES128 ECB and CBC - SHA1, SHA256 - AES128-CMAC a
drivers: dcp: add DCP support
The Data Co-Processor (DCP) provides hardware acceleraiton for cryptographic algorithms. The features of DCP are: - AES128 ECB and CBC - SHA1, SHA256 - AES128-CMAC algorithm - SRAM key storage - HUK generation
This driver adds DCP support for the following platforms: - imx6slevk - imx6sllevk - imx6ullevk - imx6ulzevk
Signed-off-by: Remi Koman <remi.koman@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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