| 90252e2a | 29-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: clock adapts to output buffer size
Changes SCMI clocks implementation to not assume the SCMI output message buffer is of a given size. Implementation still expects the output shar
drivers: scmi-msg: clock adapts to output buffer size
Changes SCMI clocks implementation to not assume the SCMI output message buffer is of a given size. Implementation still expects the output shared memory is at least large enough to hold the SCMI status information that is 32bit wide.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 57f6c5d2 | 29-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: voltage domain adapts to output buffer size
Changes SCMI voltage domain implementation to not assume the SCMI output message buffer is of a given size. Implementation still expect
drivers: scmi-msg: voltage domain adapts to output buffer size
Changes SCMI voltage domain implementation to not assume the SCMI output message buffer is of a given size. Implementation still expects the output shared memory is at least large enough to hold the SCMI status information that is 32bit wide.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 7b49ff33 | 25-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: relax constraint on output buffer size
Changes scmi_write_response() implementation to not assert the output buffer size against target payload but return a protocol error instead
drivers: scmi-msg: relax constraint on output buffer size
Changes scmi_write_response() implementation to not assert the output buffer size against target payload but return a protocol error instead since we expect shared memory size where agreed on before communication.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| d0b1e037 | 25-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: remove unused macro LEVELS_ARRAY_SIZE_MAX_2
Removes macro LEVELS_ARRAY_SIZE_MAX_2 in scmi-msg voltage-domain.c source file.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> S
drivers: scmi-msg: remove unused macro LEVELS_ARRAY_SIZE_MAX_2
Removes macro LEVELS_ARRAY_SIZE_MAX_2 in scmi-msg voltage-domain.c source file.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| d9b0a06d | 25-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: rename secure buffer size macros
Renames macro SCMI_PLAYLOAD_MAX to SCMI_SEC_PAYLOAD_SIZE and SCMI_PLAYLOAD_U32_MAX to SCMI_PAYLOAD_U32_SIZE to fix typo in macro name (play to pay
drivers: scmi-msg: rename secure buffer size macros
Renames macro SCMI_PLAYLOAD_MAX to SCMI_SEC_PAYLOAD_SIZE and SCMI_PLAYLOAD_U32_MAX to SCMI_PAYLOAD_U32_SIZE to fix typo in macro name (play to pay) and make it clear that SCMI_SEC_PAYLOAD_SIZE is the size of the secure buffer used to store a secure copy of the input SCMI message payload, that is expected small.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 5c34a982 | 25-Apr-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: scmi-msg: rename channel entry lock functions
Renames scmi_channel_set_busy() and scmi_channel_release_busy() to scmi_msg_claim_channel() and scmi_msg_release_channel(). This change also mo
drivers: scmi-msg: rename channel entry lock functions
Renames scmi_channel_set_busy() and scmi_channel_release_busy() to scmi_msg_claim_channel() and scmi_msg_release_channel(). This change also moves the implementation from smt.c to entry.c in the scmi-msg driver for alternate mailbox memory protocol support.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8f82771b | 28-Oct-2021 |
Franck LENORMAND <franck.lenormand@nxp.com> |
drivers: caam: fix cache operation on SGT table
The cache operation of the SGT table in caam_sgt_derive() was wrong and it did not take into account the CAAM "burst" defined by the value CFG_CAAM_SG
drivers: caam: fix cache operation on SGT table
The cache operation of the SGT table in caam_sgt_derive() was wrong and it did not take into account the CAAM "burst" defined by the value CFG_CAAM_SGT_ALIGN. The cache operation of the SGT table in caam_sgt_cache_op() is done correctly however.
This patch adds caam_sgt_entries_cache_clean() to do this operation and avoid implementation errors.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 2e1b85fe | 04-Apr-2022 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
tpm2: Add TPM2 as PCR provider to TCG eventlog parsing framework
TCG eventlog parsing framework parses the eventlog and extends the PCR's. For this, it needs a provider for PCR's. Register TPM2 as a
tpm2: Add TPM2 as PCR provider to TCG eventlog parsing framework
TCG eventlog parsing framework parses the eventlog and extends the PCR's. For this, it needs a provider for PCR's. Register TPM2 as a provider to this framework.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 776670df | 30-Mar-2022 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
tpm2: Add commands to GetCapability, Read/Extend PCR
Add support for TPM2_PCR_{Read/Extend} and TPM2_GetCapability. TPM uses PCR for integrity collections. Add support to read and extend PCR's. For
tpm2: Add commands to GetCapability, Read/Extend PCR
Add support for TPM2_PCR_{Read/Extend} and TPM2_GetCapability. TPM uses PCR for integrity collections. Add support to read and extend PCR's. For PCR's some generic information like number of banks, number of PCR's, supported and active algorithms etc. is required which can be obtained from TPM using TPM2_GetCapability command. This information is required at lot of places, so save the basic capability information with tpm2_chip.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| b683df79 | 23-Mar-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx_ocotp: initialize OCOTP driver earlier
Initialize the OCOTP driver earlier with service_init() instead of driver_init().
With CFG_CORE_HUK_SUBKEY_COMPAT=y, tee_fs_init_key_manager() an
drivers: imx_ocotp: initialize OCOTP driver earlier
Initialize the OCOTP driver earlier with service_init() instead of driver_init().
With CFG_CORE_HUK_SUBKEY_COMPAT=y, tee_fs_init_key_manager() and consequently tee_otp_get_die_id() get executed earlier than the OCOTP driver initialization. tee_fs_init_key_manager() is called by service_init_late() routine.
On platforms featuring the OCOTP driver, the function tee_otp_get_die_id() relies on the driver to be initialized.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 00df7d99 | 24-Mar-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: crypto: remove unnecessary header
Remove the following header: * utee_defines.h
Fixes: f5a70e3e ("drivers: crypto: generic resources for crypto device driver - RSA") Signed-off-by: Clement
drivers: crypto: remove unnecessary header
Remove the following header: * utee_defines.h
Fixes: f5a70e3e ("drivers: crypto: generic resources for crypto device driver - RSA") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 74bd878e | 24-Mar-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: crypto: remove unnecessary header
Remove the following header: * utee_defines.h
Fixes: e43ab7a8 ("core: driver: generic resources for crypto cipher driver") Signed-off-by: Clement Faure <
drivers: crypto: remove unnecessary header
Remove the following header: * utee_defines.h
Fixes: e43ab7a8 ("core: driver: generic resources for crypto cipher driver") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 27f7b883 | 24-Mar-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: remove unnecessary header
Remove the following header: * caam_utils_mem.h
Fixes: 2d7a8964 ("driver: implement CAAM driver") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acke
drivers: caam: remove unnecessary header
Remove the following header: * caam_utils_mem.h
Fixes: 2d7a8964 ("driver: implement CAAM driver") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| ca430e6e | 24-Mar-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: fix potential memory leak
Free CAAM buffer pabufs before exiting the function in case of an error.
Fixes: 38923d487 ("drivers: caam: implement CAAM DMA Object") Signed-off-by: Clemen
drivers: caam: fix potential memory leak
Free CAAM buffer pabufs before exiting the function in case of an error.
Fixes: 38923d487 ("drivers: caam: implement CAAM DMA Object") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 1ae3ec2d | 24-Mar-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: avoid arithmetic operation for pointer assignment
To parse the pointer array priv->sgtdata[], use this syntax array[idx] instead of array + idx. The new syntax is easier to read and l
drivers: caam: avoid arithmetic operation for pointer assignment
To parse the pointer array priv->sgtdata[], use this syntax array[idx] instead of array + idx. The new syntax is easier to read and less prone to errors.
Fixes: 38923d48 ("drivers: caam: implement CAAM DMA Object") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| ca1d8e13 | 25-Apr-2022 |
Neal Liu <neal_liu@aspeedtech.com> |
drivers: crypto: aspeed: hace: fix digest incorrect problem
1. The processing status variable is not set to TEE_SUCCESS if everything works fine. 2. DMA memory needs physically contiguous memory. Al
drivers: crypto: aspeed: hace: fix digest incorrect problem
1. The processing status variable is not set to TEE_SUCCESS if everything works fine. 2. DMA memory needs physically contiguous memory. Allocate aligned DMA memory and copy data from/to DMA memory to make sure consistency of data.
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 0c2a8f2f | 25-Apr-2022 |
Neal Liu <neal_liu@aspeedtech.com> |
drivers: crypto: aspeed: hace: resolve build issues
Resolve various build and typo issues.
Fixes: commit e752c173aa0f ("crypto/aspeed: ast2600: Add HACE HW hash support") Signed-off-by: Neal Liu <n
drivers: crypto: aspeed: hace: resolve build issues
Resolve various build and typo issues.
Fixes: commit e752c173aa0f ("crypto/aspeed: ast2600: Add HACE HW hash support") Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 0e467cb0 | 13-Apr-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: add JR interrupt only if CFG_CAAM_ITR=y
Adding the JR interrupt in the OPTEE CAAM driver, even if not used in OPTEE, prevents the Linux CAAM driver from using the JR interrupt on plat
drivers: caam: add JR interrupt only if CFG_CAAM_ITR=y
Adding the JR interrupt in the OPTEE CAAM driver, even if not used in OPTEE, prevents the Linux CAAM driver from using the JR interrupt on platforms sharing the same line of interruption for all job rings.
To dequeue job from the job ring, the Linux CAAM driver would pull the number of jobs done from the output ring slot full register.
The fix is to add the JR interrupt only if CFG_CAAM_ITR=y. This allows the Linux CAAM driver to dequeue jobs faster than polling from a register.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 497dbec8 | 05-Apr-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: fix function definition when CFG_CAAM_NO_ITR=y
There is a bug in the CAAM JR interruption enablement logic. When CFG_CAAM_NO_ITR=y, the JR interruptions are used and when CFG_CAAM_NO_
drivers: caam: fix function definition when CFG_CAAM_NO_ITR=y
There is a bug in the CAAM JR interruption enablement logic. When CFG_CAAM_NO_ITR=y, the JR interruptions are used and when CFG_CAAM_NO_ITR=n, the JR interruptions are not used.
Even with this wrong logic, the CAAM is still able to enqueue jobs. When no JR interruptions are received, the CAAM will manually dequeue jobs from the jobring by checking the number of jobs done in the output ring slots full register.
CAAM JR interruptions are not mandatory for the CAAM to work properly but it makes the dequeuing faster than polling the output ring slot full register.
To avoid confusion, replace CFG_CAAM_NO_ITR with CFG_CAAM_ITR. The CFG_CAAM_ITR is enabled by default and platforms not using the JR interruptions would have this flag disabled instead.
Fixes: 3f45afc31 ("drivers: caam: disable the use of interrupts for some platforms") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 627f246d | 30-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: Fix check for assigned-clock-rates index
Index should actually be strictly less than rate_len. Fix this which might happen with the following description:
assigned-clock = <foo>, <bar
drivers: clk: Fix check for assigned-clock-rates index
Index should actually be strictly less than rate_len. Fix this which might happen with the following description:
assigned-clock = <foo>, <bar>; assigned-clock-parents = <foo_parent>, <bar_parent>; assigned-clock-rates = <1000>;
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 552e0c1c | 26-Jul-2021 |
Clement Faure <clement.faure@nxp.com> |
drivers: tzc380: fix the lockdown range register value
This register controls the range of regions that are locked down. The number of regions to lockdown are defined in [1]: lockdown_range[3:0] and
drivers: tzc380: fix the lockdown range register value
This register controls the range of regions that are locked down. The number of regions to lockdown are defined in [1]: lockdown_range[3:0] and its value goes from b0000 to b1111.
If the goal of tzc_regions_lockdown() is to lock all regions supported by the platforms, then the value of lockdown_range[3:0] should be equal to no_of_regions[3:0] of the configuration register [2].
Currently, tzc.num_regions is used to defined the lockdown range which is incorrect because it has been incremented during initialization. Fix the issue by decrementing tzc.num_regions before the configuration of lockdown_range[3:0].
Link: [1] https://developer.arm.com/documentation/ddi0431/c/programmers-model/register-descriptions/lockdown-range-register Link: [2] https://developer.arm.com/documentation/ddi0431/c/programmers-model/register-descriptions/configuration-register Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 9cb0d516 | 30-Jun-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: stpmic1: export regulators API in a specific header file
Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator interface.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
drivers: stpmic1: export regulators API in a specific header file
Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator interface.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| a9edcef3 | 25-Jan-2022 |
Vanessa Maegima <vanessa.maegima@foundries.io> |
drivers: imx_i2c: add support for MX8MP
Add I2C driver support for iMX8MP.
Signed-off-by: Vanessa Maegima <vanessa.maegima@foundries.io> Acked-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jo
drivers: imx_i2c: add support for MX8MP
Add I2C driver support for iMX8MP.
Signed-off-by: Vanessa Maegima <vanessa.maegima@foundries.io> Acked-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
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| 97d74896 | 09-Mar-2022 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
drivers/tpm2: Startup TPM when chip is registered
When tpm2 chip is registered, call the initialization sequence of tpm to do self test and startup the tpm chip.
Signed-off-by: Ruchika Gupta <ruchi
drivers/tpm2: Startup TPM when chip is registered
When tpm2 chip is registered, call the initialization sequence of tpm to do self test and startup the tpm chip.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8c2e0b2e | 25-Feb-2022 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
drivers/tpm2: Add basic structure for commands
Add infrastructure for TPM2 commands based on [1].
Few basic commands like TPM2 Startup and Selftest. These will be used by device driver during initi
drivers/tpm2: Add basic structure for commands
Add infrastructure for TPM2 commands based on [1].
Few basic commands like TPM2 Startup and Selftest. These will be used by device driver during initialization.
[1] Trusted Platform Module Library Part 3: Commands Family “2.0” Level 00 Revision 01.59
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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