drivers: crypto: stm32_cryp: remove reset binding requirements

Remove panic during probe when "resets" property is not found because
it's optional in most cases.

Signed-off-by: Thomas Bourgoin <tho

drivers: crypto: stm32_cryp: remove reset binding requirements

Remove panic during probe when "resets" property is not found because
it's optional in most cases.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: hisilicon: init HPRE hardware block

The HiSilicon HPRE is a High Performance RSA Engine.
This module implement the hardware initialization of
the HPRE.

Signed-off-by: loubaihui <lo

drivers: crypto: hisilicon: init HPRE hardware block

The HiSilicon HPRE is a High Performance RSA Engine.
This module implement the hardware initialization of
the HPRE.

Signed-off-by: loubaihui <loubaihui1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: regulator: use mutex_pm_aware

Use newly introduced struct mutex_pm_aware semaphore to protect
regulator accesses.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Eti

drivers: regulator: use mutex_pm_aware

Use newly introduced struct mutex_pm_aware semaphore to protect
regulator accesses.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: replace clock main spinlock with a mutex

Change clock framework lock from an interrupts masked spinning lock
to a mutex. This allows the clock framework to better handle slow
stabilizi

drivers: clk: replace clock main spinlock with a mutex

Change clock framework lock from an interrupts masked spinning lock
to a mutex. This allows the clock framework to better handle slow
stabilizing clocks as PLLs without masking the system interrupt
which can have side effects on the REE or even the TEE.

To support clock accesses during low power state transition sequences
while non-secure world is no operating, the lock is not taken when
the execution is not in the scope of a TEE thread.

This change is not expected to impact supported platforms that currently
only access clock operation from thread contexts or atomic PM sequences.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: replace REGISTER_TIME_SOURCE()

Remove REGISTER_TIME_SOURCE() and implement tee_time_get_sys_time() and
tee_time_get_sys_time_protection_level() directly in the file where
REGISTER_TIME_SOURCE(

core: replace REGISTER_TIME_SOURCE()

Remove REGISTER_TIME_SOURCE() and implement tee_time_get_sys_time() and
tee_time_get_sys_time_protection_level() directly in the file where
REGISTER_TIME_SOURCE() was used previously.

By avoiding indirect calls the linker can optimize the dependency tree
properly and we can remove the DECLARE_KEEP_PAGER() directive needed for
arm_cntpct_time_source.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: clk-stm32mp13: fix memory corruption on oscillator parent

Fix oscillators struct clk instances for STM32MP13 clock driver. These
clocks have 1 parent that is set during driver initiali

drivers: clk: clk-stm32mp13: fix memory corruption on oscillator parent

Fix oscillators struct clk instances for STM32MP13 clock driver. These
clocks have 1 parent that is set during driver initialization, based on
device tree content, whereas referred bugged commit defined 0 parents
and did not allocate memory for the parent reference.

Fixes: 95f2142bf848 ("drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired")
Tested-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator leve

drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator level value depends on the parent regulator
(supply). It is up the regulator drivers to cache or not this
value in their private data if applicable.

Fixes: 1a3d3273040b ("drivers: regulator framework")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ac

drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: add sama7g5 clock description

Define PLL, master, system, peripheral, generic clocks for sama7g5 and
register the clocks to clock provider.

Signed-off-by: Tony Han <tony.han@micr

drivers: clk: sam: add sama7g5 clock description

Define PLL, master, system, peripheral, generic clocks for sama7g5 and
register the clocks to clock provider.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: nvmem: add nvmem-huk driver

This driver is meant to read the OTP unique hardware key from a
NVMEM controller. It uses the nvmem framework to read the NVMEM
cells from the device tree.

Sign

drivers: nvmem: add nvmem-huk driver

This driver is meant to read the OTP unique hardware key from a
NVMEM controller. It uses the nvmem framework to read the NVMEM
cells from the device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: nvmem: add nvmem-die-id driver

This driver is meant to read the die id from a NVMEM controller.
It uses the nvmem framework to read the NVMEM cells from the
device tree.

Signed-off-by: Tho

drivers: nvmem: add nvmem-die-id driver

This driver is meant to read the die id from a NVMEM controller.
It uses the nvmem framework to read the NVMEM cells from the
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Implement semihosting based console driver for log

Implement a simple console driver which uses semihosting operations to
read/write the trace messages. There are two paths to output the tr

drivers: Implement semihosting based console driver for log

Implement a simple console driver which uses semihosting operations to
read/write the trace messages. There are two paths to output the trace
messages:
- If the caller of semihosting_console_init() provides the path of the
file, the driver will try to open that file, and output the log to
that host side file.
- If the caller of semihosting_console_init() does not provide the path
of the file, the driver will connect the console to the host debug
console directly.

If CFG_SEMIHOSTING_CONSOLE is enabled, OP-TEE will try to initialize the
semihosting console driver by given CFG_SEMIHOSTING_CONSOLE_FILE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: clk: get stm32mp13 PLL output clock duty cycle

Implement get_duty_cycle clock operation for STM32MP13 PLL output clocks.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Sign

drivers: clk: get stm32mp13 PLL output clock duty cycle

Implement get_duty_cycle clock operation for STM32MP13 PLL output clocks.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: set stm32mp13 clock flags

On STM32MP13 SoC, setting PLL1P, PLL1P_DIV, MPU, AXI and MLAHB clocks
rate must be handled from their respective parent clock. Set flag
CLK_SET_RATE_PARENT fo

drivers: clk: set stm32mp13 clock flags

On STM32MP13 SoC, setting PLL1P, PLL1P_DIV, MPU, AXI and MLAHB clocks
rate must be handled from their respective parent clock. Set flag
CLK_SET_RATE_PARENT for these clocks.

On STM32MP13 SoC, MPU, AXI and MLAHB clocks are internal bus clocks
that must not be disabled even when we re-parent them. Set flag
CLK_SET_PARENT_PRE_ENABLE for these clocks.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: pre-enable new parent on clock re-parent

Add new clock flag CLK_SET_PARENT_PRE_ENABLE for when an already
enabled clock is re-parented and the new parent clock must be enabled
before w

drivers: clk: pre-enable new parent on clock re-parent

Add new clock flag CLK_SET_PARENT_PRE_ENABLE for when an already
enabled clock is re-parented and the new parent clock must be enabled
before we switch of parents.

This is needed for some system clocks that cannot be disabled, for
example an interconnect AXI bus clock or a CPU clock.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: get linear rates description

Implement clk_get_rates_steps() clock API function to get the supported
clock rates description as a triplet min/max/step. This function can be
used in the

drivers: clk: get linear rates description

Implement clk_get_rates_steps() clock API function to get the supported
clock rates description as a triplet min/max/step. This function can be
used in the scope of SCMI communication where a clock can report a
linear rate list without listing all supported clock is an array
which size could be quite big.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: enable clock on rate change

Add new clock flag CLK_SET_RATE_UNGATE for clocks that must be
enabled in order to change their rate.

Reviewed-by: Gatien Chevallier <gatien.chevallier@fos

drivers: clk: enable clock on rate change

Add new clock flag CLK_SET_RATE_UNGATE for clocks that must be
enabled in order to change their rate.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: change parent clock rate if needed

Add clock flag CLK_SET_RATE_PARENT for clocks for which rate change
request must be propagated to the parent clock.

Reviewed-by: Gatien Chevallier <

drivers: clk: change parent clock rate if needed

Add clock flag CLK_SET_RATE_PARENT for clocks for which rate change
request must be propagated to the parent clock.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: Get duty cycle from parent clock

Add CLK_DUTY_CYCLE_PARENT clock flag for clock which duty cycle
information needs to be retrieved for the clock parent.

Reviewed-by: Gatien Chevallier

drivers: clk: Get duty cycle from parent clock

Add CLK_DUTY_CYCLE_PARENT clock flag for clock which duty cycle
information needs to be retrieved for the clock parent.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: Add clock duty cycle

Implement reading a clock duty cycle with new clock API function
clk_get_duty_cycle() and clock operation handle ::clk_get_duty_cycle.
When a clock does not provid

drivers: clk: Add clock duty cycle

Implement reading a clock duty cycle with new clock API function
clk_get_duty_cycle() and clock operation handle ::clk_get_duty_cycle.
When a clock does not provide the operation, it is assumed that the clock
has a 50% duty cycle.

Clock duty cycle information is used for example for some analog-digital
conversion peripheral. This new API function is also expected to be used
by SCMI clock service introduced in the SCMI specification v3.2 [1]
this allow to expose duty cycle service to SCMI clients.

Link: https://developer.arm.com/documentation/den0056/e/ [1]
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.

drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support generic clock for sama7g5

Add a mux table for select from different generic clock source.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fori

drivers: clk: sam: update to support generic clock for sama7g5

Add a mux table for select from different generic clock source.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support main system bus clock for sama7g5

Add functions for configuring sama7g5 main system bus clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome

drivers: clk: sam: update to support main system bus clock for sama7g5

Add functions for configuring sama7g5 main system bus clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updat

core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updates are still being propagated. Add checks for this
after each write to GICR_ICENABLER0 to make sure that the system is
consistent before continuing.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be sync

core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be synchronized to all CPUs in the same way. Add support to
synchronize needed PPI configuration to other CPUs.

The configuration that needs to be synchronized to other CPUs should
ideally not be changed once the primary CPU has booted. So add a check
in gic_op_enable() to catch this.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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