gpio: support multiple instances

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: add spi framework and pl022 driver

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklan

drivers: add spi framework and pl022 driver

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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Add support for Spreadtrum SC9860(alias whale2) board

make PLATFORM=sprd-sc9860 [CFG_ARM64_core=y]

Signed-off-by: Aijun Sun <aijun.sun@spreadtrum.com>
Reviewed-by: Jerome Forissier <jerome.forissie

Add support for Spreadtrum SC9860(alias whale2) board

make PLATFORM=sprd-sc9860 [CFG_ARM64_core=y]

Signed-off-by: Aijun Sun <aijun.sun@spreadtrum.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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Add Cadence UART driver

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Revi

Add Cadence UART driver

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fixes undefined behavior

Fixes undefined behavior detected with CFG_CORE_SANITIZE_UNDEFINED=y

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@l

core: fixes undefined behavior

Fixes undefined behavior detected with CFG_CORE_SANITIZE_UNDEFINED=y

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: gpio: fix write8 function argument order

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: add gpio framework and pl061 driver

Suggested-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklande

drivers: add gpio framework and pl061 driver

Suggested-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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core: add interrupt framework

Adds interrupt frameworks and adjusts gic driver to fit in.

Update plat-vexpress and sunxi platforms to initialize gic with slightly
modified interface.

Reviewed-by:

core: add interrupt framework

Adds interrupt frameworks and adjusts gic driver to fit in.

Update plat-vexpress and sunxi platforms to initialize gic with slightly
modified interface.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers/core/gic.c: Set priority mask to allow NS interrupts

The non-secure world's view of interrupt priorities only allows
it to set priorities between 0x80 and 0xff. This means that the
secure wo

drivers/core/gic.c: Set priority mask to allow NS interrupts

The non-secure world's view of interrupt priorities only allows
it to set priorities between 0x80 and 0xff. This means that the
secure world has to set the GICC_PMR (priority mask register) to
a value that allows NS interrupts, otherwise the non-secure
world will never see interrupts and has no way to set the
priorities so that it will ever see them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers/core/gic.c: Fix indentation in gic_cpu_init()

The indentation in gic_cpu_init() is using spaces rather than
tabs. Since it's a very short function and we're about to add
some code to it, fix

drivers/core/gic.c: Fix indentation in gic_cpu_init()

The indentation in gic_cpu_init() is using spaces rather than
tabs. Since it's a very short function and we're about to add
some code to it, fix the indentation first.

Fix a comment typo while we're here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: imx: add i.MX 6UltraLite and EVK board support

The i.MX 6UltraLite[1] is a high performance, ultra-efficient processor
family featuring an advanced implementation of a single ARM® Cortex®-A7
co

arm: imx: add i.MX 6UltraLite and EVK board support

The i.MX 6UltraLite[1] is a high performance, ultra-efficient processor
family featuring an advanced implementation of a single ARM® Cortex®-A7
core.

This patch add i.MX 6Ulralite EVK board support:
1. Add a uart driver for i.MX platforms
2. Introduce plat-imx for i.MX platforms
3. Introduce i.MX6 UltraLite platform
4. This patch has been tested using the following step,
4.1. build step:
PLATFORM_FLAVOR=mx6ulevk make ARCH=arm PLATFORM=imx
${CROSS_COMPILE}-objcopy -O binary out/arm-plat-imx/core/tee.elf optee.bin
copy optee.bin to the first partition of SD card which is used for boot.
4.2. Boot setting in uboot:
run loadfdt;
run loadimage;
fatload mmc 1:1 0x9c100000 optee.bin;
run mmcargs;
bootz ${loadaddr} - ${fdt_addr};
5. pass xtest

Note:
CAAM is not implemented now, this will be added later.

[1] http://www.freescale.com/webapp/sps/site/prod_summary.jsp?
code=i.MX6UL&tid=redI.MX6UL-FAMILY&uc=true&lang_cd=en

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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Add fsl ls1021a platform support.

Added plat-ls, with initial support for fsl ls1021a platform.
Added uart driver (ns16550).

Signed-off-by: Sumit Garg <b49020@freescale.com>
Reviewed-by: Jens Wikla

Add fsl ls1021a platform support.

Added plat-ls, with initial support for fsl ls1021a platform.
Added uart driver (ns16550).

Signed-off-by: Sumit Garg <b49020@freescale.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core pl011: enable RT interrupt

Enables Receive Timeout interrupt when initializing a PL011 uart. This
will generate an interrupt very soon after each key press in the
terminal.

Signed-off-by: Jens

core pl011: enable RT interrupt

Enables Receive Timeout interrupt when initializing a PL011 uart. This
will generate an interrupt very soon after each key press in the
terminal.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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Mediatek mt8173 platform support

Add support for Mediatek mt8173 platform with 32bit
and 64bit OP-TEE OS. Due to Mediatek ATF firmware
limitation, this commit only tested with 64bit OP-TEE OS.

Sign

Mediatek mt8173 platform support

Add support for Mediatek mt8173 platform with 32bit
and 64bit OP-TEE OS. Due to Mediatek ATF firmware
limitation, this commit only tested with 64bit OP-TEE OS.

Signed-off-by: James Kung <james.kung@linaro.org>
Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: James Kung <james.kung@linaro.org> (MT8173 EVB)
Tested-by: SY Chiu <sy.chiu@linaro.org> (MT8173 EVB)

NOTE: To test this on MT8173 EVB, you need to update firmware
please refer to https://github.com/m943040028/evb-utils

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select base types based on ILP32 and LP64 defines

* Selects base types base on the __ILP32__ and __LP64__ defines
* Fixes warnings from change of base types

Signed-off-by: Jens Wiklander <jens.wikl

select base types based on ILP32 and LP64 defines

* Selects base types base on the __ILP32__ and __LP64__ defines
* Fixes warnings from change of base types

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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Convert configuration variables to CFG_* name

- Rename configuration variables that do not follow the CFG_* convention
- Delete useless -D<VAR> compiler flags
- Slightly reformat mk/conf.mk, add com

Convert configuration variables to CFG_* name

- Rename configuration variables that do not follow the CFG_* convention
- Delete useless -D<VAR> compiler flags
- Slightly reformat mk/conf.mk, add comments

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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UART cleaning

- Rename core/include/drivers/{uart.h -> pl011.h} and
core/drivers/{uart.c -> pl011.c}. Use pl011_ prefix.
- Remove WITH_UART_DRV, which was used to enable pl011 on vexpress platform

UART cleaning

- Rename core/include/drivers/{uart.h -> pl011.h} and
core/drivers/{uart.c -> pl011.c}. Use pl011_ prefix.
- Remove WITH_UART_DRV, which was used to enable pl011 on vexpress platforms
and sunxi_uart on sunxi platform. Replace it with CFG_PL011 and
CFG_SUNXI_UART.
- Move platform-specific (STM) code in core/arch/arm32/tee/init.c (which
was guarded by #ifndef WITH_UART_DRV) to core/arch/arm32/plat-stm/tz_init.S.
- Move core/arch/arm32/include/kernel/asc.h to core/arch/arm32/plat-stm.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (FVP)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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Add plat-sunxi

Initial version support for Allwinner A80 platform.
Allwinner A80 is big.little archtecture with 4*A7 + 4*A15,
Support Trustzone tech and secureboot inside hardware.
plat-sunxi suppor

Add plat-sunxi

Initial version support for Allwinner A80 platform.
Allwinner A80 is big.little archtecture with 4*A7 + 4*A15,
Support Trustzone tech and secureboot inside hardware.
plat-sunxi support features:
1.Clone plat-sunxi from plat-vexpress;
2.Secure bootloader reserved 64MB secure DRAM for optee_os;
3.Support SMP secondary cpu secure stage bootup;
4.Add uart driver to core/driver/*;
5.Support GIC driver initialization.
The porting work test on Optimus board, with allwinner A80 chip.

Signed-off-by: sunny <sunny@allwinnertech.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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driver/gic: add gic_cpu_init interface.

The interface mainly use for secondary cpu bootup.
When secondary cpu bootup, It will initialize per-cpu gic-cpu-interface.
The gic_cpu_init main work include

driver/gic: add gic_cpu_init interface.

The interface mainly use for secondary cpu bootup.
When secondary cpu bootup, It will initialize per-cpu gic-cpu-interface.
The gic_cpu_init main work include:
1.Set the per-cpu interrupts as Group1;
2.Enable Group0-interrupts/Group1-interrupts/FIQEn.

Signed-off-by: sunny <sunny@allwinnertech.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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Merge tee_{core,uta}_trace.h into libutil

Merges tee_core_trace.h and tee_uta_trace.h into a common trace.h
in libutil. Since the trace functions now resides libutil they have
to rely on core and li

Merge tee_{core,uta}_trace.h into libutil

Merges tee_core_trace.h and tee_uta_trace.h into a common trace.h
in libutil. Since the trace functions now resides libutil they have
to rely on core and libutee to provide functions to print to the
log device.

* Keeps compatible interface from tee_kta_trace.h
* Adds TAMSG() and TAMSG_RAW() to log TA related events
* Removes the TRACE_ALWAYS level

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt platform)
Reviewed-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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uart: add baudrate and clock freqency to uart_init

Adds baudrate and clock frequency as agruments to uart_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand

uart: add baudrate and clock freqency to uart_init

Adds baudrate and clock frequency as agruments to uart_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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Drivers gic and uart are optional

Platforms stm do not use gic and uart drivers, whereas vexpress (fvp / qemu)
does. So the conf.mk of the latter case defines the following:
WITH_UART_DRV := y

Drivers gic and uart are optional

Platforms stm do not use gic and uart drivers, whereas vexpress (fvp / qemu)
does. So the conf.mk of the latter case defines the following:
WITH_UART_DRV := y
WITH_GIC_DRV := y

Reviewed-by: Joakim Bech joakim.bech@linaro.org
Reviewed-by: Jens Wiklander jens.wiklander@linaro.org
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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fvp: enable uart1 fiq

Configures UART1/GIC to generate a FIQ when there's input on
UART1.

gic: bugfix probe_max_it

Add GIC status dump utility

- fixed fvp gic cpu interface and distrubtor offset
- added new mapping for distrubtor
- add utility to dump gic status