drivers: ele: update session open command parameters

Update session open command parameters to be compatible with
ELE FW API doc

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jen

drivers: ele: update session open command parameters

Update session open command parameters to be compatible with
ELE FW API doc

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: allocate data in heap for HUK derivation

Use the heap and the ELE memory allocator instead of using the stack.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahi

drivers: ele: allocate data in heap for HUK derivation

Use the heap and the ELE memory allocator instead of using the stack.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: use the baseline API to retrieve the UID

Use the baseline API instead of the HSM to retrieve the UID. These two
API calls are duplicates and the HSM call is soon deprecated.

Signed-of

drivers: ele: use the baseline API to retrieve the UID

Use the baseline API instead of the HSM to retrieve the UID. These two
API calls are duplicates and the HSM call is soon deprecated.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: disable ASLR for imx8ulp

On imx8ulp, the RNG code from ELE is not available at resume. Disable
the ASLR feature and make it available for imx93 only.

Signed-off-by: Clement Faure <cle

drivers: ele: disable ASLR for imx8ulp

On imx8ulp, the RNG code from ELE is not available at resume. Disable
the ASLR feature and make it available for imx93 only.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: add memory management functions

Add memory management function

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Et

drivers: ele: add memory management functions

Add memory management function

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: getting common macros and functions in header file

Taking out macros and functions from c file and put them in
header file for being used by the other files of crypto driver.

Signed-o

drivers: ele: getting common macros and functions in header file

Taking out macros and functions from c file and put them in
header file for being used by the other files of crypto driver.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: move ELE to a dedicated directory

Created a new folder in core/drivers/crypto named ele
and moved ele.c in that folder.
This is done for making the base for further crypto driver
based

drivers: ele: move ELE to a dedicated directory

Created a new folder in core/drivers/crypto named ele
and moved ele.c in that folder.
This is done for making the base for further crypto driver
based on ELE.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: add RISC-V APLIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the APLIC, which can serve as a new external interrupt controller to
replace the

drivers: add RISC-V APLIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the APLIC, which can serve as a new external interrupt controller to
replace the original Platform-Level Interrupt Controller (PLIC) or as a
device to convert wired interrupts into message-signaled interrupts
(MSIs) and forward them to the Incoming MSI Controller (IMSIC).

The APLIC driver supports both "direct delivery mode" and
"MSI delivery mode." Use the `CFG_RISCV_APLIC` flag to enable the
APLIC driver in "direct delivery mode," and use the
`CFG_RISCV_APLIC_MSI` flag to enable the APLIC driver in "MSI
delivery mode" when selecting `CFG_RISCV_IMSIC`.

APLIC initialization can be done through the device tree.

For more details, see: https://github.com/riscv/riscv-aia

Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add RISC-V IMSIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records i

drivers: add RISC-V IMSIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records incoming message-signaled interrupts (MSIs).

This commit enables the initialization of the IMSIC based on the device
tree and adds control and status registers (CSRs) for indirect access to
the IMSIC as well as for reading interrupt identities.

Use the `CFG_RISCV_IMSIC` flag to control whether to build this driver.

For more details, see: https://github.com/riscv/riscv-aia

Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: do not acknowledge end of interrupt for special GIC interrupt IDs

According to the ARM documentation for GICV2/3/4, there is no need to
write to the end of interrupt register for some special

core: do not acknowledge end of interrupt for special GIC interrupt IDs

According to the ARM documentation for GICV2/3/4, there is no need to
write to the end of interrupt register for some special IDs. Apply this
recommendation to avoid writing to IO memory in this time sensitive
sequence.

Also distinguish unhandled interrupts with an error log.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal

plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal Access was caught and print the SERC register and panic()
if that is the case.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: imx: rngb: early initialization

The RNGB module must be ready during init_tee_runtime to provide a
random stack canary value during bootup.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundr

drivers: imx: rngb: early initialization

The RNGB module must be ready during init_tee_runtime to provide a
random stack canary value during bootup.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: interrupt: rename .add handler to .configure

Rename field add of struct itr_ops to configure for consistency
since that handler is used the configure the interrupt. Update
existing interrupt d

core: interrupt: rename .add handler to .configure

Rename field add of struct itr_ops to configure for consistency
since that handler is used the configure the interrupt. Update
existing interrupt drivers accordingly.

By the way fix inline comment spelling typo (s/contrainsts/constraints/).

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_risab: add .set_memory_conf ops

Add the .set_memory_conf ops to be able to reconfigure memory regions
protected by RISABs dynamically.

Factorize the RIF configuration application.

S

drivers: stm32_risab: add .set_memory_conf ops

Add the .set_memory_conf ops to be able to reconfigure memory regions
protected by RISABs dynamically.

Factorize the RIF configuration application.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: rework regs_access_granted()

Rework regs_access_granted() to always authorize access to RISAB1/2
that can only be accessed by the Cortex-A35.

Also fix the sequence by isolatin

drivers: stm32_risab: rework regs_access_granted()

Rework regs_access_granted() to always authorize access to RISAB1/2
that can only be accessed by the Cortex-A35.

Also fix the sequence by isolating the case where the CID filtering is
not enabled.

Fixes: c413678c6ca6 ("drivers: stm32_risab: add RISAB internal memory firewall driver")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: stm32_etzpc: remove header file

Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c

By the way, al

drivers: firewall: stm32_etzpc: remove header file

Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c

By the way, also remove inclusion of stm32mp15-etzpc.h DT bindings
header file from stm32_rng.c where it is not needed.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: gic: minor coding style fixes

Fix minor issues coding style issue for uninitialized local variable
and trace message formatting. No functional change.

Signed-off-by: Etienne Carriere <etie

drivers: gic: minor coding style fixes

Fix minor issues coding style issue for uninitialized local variable
and trace message formatting. No functional change.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: gic: allow detection type configuration

Allow consumers to configure SPI interrupts when the provided type
is not IRQ_TYPE_NONE. The allowed value are then IRQ_TYPE_EDGE_RISING
and IRQ_TYPE

drivers: gic: allow detection type configuration

Allow consumers to configure SPI interrupts when the provided type
is not IRQ_TYPE_NONE. The allowed value are then IRQ_TYPE_EDGE_RISING
and IRQ_TYPE_LEVEL_HIGH, as per Arm GIC specification.

This change fixes an issue when using interrupt_dt_get_by_index()
or interrupt_dt_get_by_name() since these API functions tell the
interrupt is configured from DT phandle arguments whereas GIC driver
did not consider the interrupt detection type even if set in the
consumer DT node property.

Fixes: 14885eb1688b ("drivers: gic: register to dt_driver")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_rifsc: add RISAL support for stm32mp25x platforms

Add RISAL driver support.

RISAL is a sub-feature of the RISFC which is responsible for the
isolation of hardware resources like memo

drivers: stm32_rifsc: add RISAL support for stm32mp25x platforms

Add RISAL driver support.

RISAL is a sub-feature of the RISFC which is responsible for the
isolation of hardware resources like memory or peripherals. RISALs are
simplified version of the RISAFs firewall controllers and cover the
LPSRAM1/2/3 embedded memories.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Gwenael Treuveur <gwenael.treuveur@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risaf: upgrade RISAF as a firewall controller

Register RISAF instances as firewall controllers with ops:
-acquire_memory_access() that checks if OP-TEE can access a region
specified i

drivers: stm32_risaf: upgrade RISAF as a firewall controller

Register RISAF instances as firewall controllers with ops:
-acquire_memory_access() that checks if OP-TEE can access a region
specified in a firewall query.
-set_conf() that allows the reconfiguration of a region.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: dra7_rng: Change dra7_rng_init to service_init_crypto

Since commit 11d8578d93f0 ("core: arm: call call_driver_initcalls()
late"), driver_init is deferred and thread_update_canaries tries to

drivers: dra7_rng: Change dra7_rng_init to service_init_crypto

Since commit 11d8578d93f0 ("core: arm: call call_driver_initcalls()
late"), driver_init is deferred and thread_update_canaries tries to get
random_stack_canaries which requires the TRNG driver to be setup. Since
it was being setup as part of driver_init, it lead to crash on DRA7
platforms.

Change driver_init to service_init_crypto which is meant to be used for
initialization of crypto operations.

While here, add an assert that checks for DRA7 TRNG being used before
initialization is complete.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_stgen: fix type in debug trace

Fix the type in a debug trace in stm32_stgen_pm_resume() to fix a
compilation warning.

Fixes: b0b019b81314 ("drivers: counter: stm32_stgen: add STGEN d

drivers: stm32_stgen: fix type in debug trace

Fix the type in a debug trace in stm32_stgen_pm_resume() to fix a
compilation warning.

Fixes: b0b019b81314 ("drivers: counter: stm32_stgen: add STGEN driver")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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crypto: stm32: use PKA IP for ECC algorithm

Add PKA IP drivers, and add hooks in OP-TEE crypto framework to use
PKA IP to do ECC process.

Truncate hash during ECDSA signature according to the NIST

crypto: stm32: use PKA IP for ECC algorithm

Add PKA IP drivers, and add hooks in OP-TEE crypto framework to use
PKA IP to do ECC process.

Truncate hash during ECDSA signature according to the NIST
recommendation:
https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.186-5.pdf

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_i2c: use compatible st,stm32mp15-i2c-non-secure

Change STM32 I2C driver to rely on the compatible DT property of the
node to store whether the bus is expected assigned to secure or
no

drivers: stm32_i2c: use compatible st,stm32mp15-i2c-non-secure

Change STM32 I2C driver to rely on the compatible DT property of the
node to store whether the bus is expected assigned to secure or
non-secure world. Using a non-secure I2C bus in OP-TEE on stm32mp1
platforms is something expected only on STM32MP15 variant for
compatibility with platform already supported in upstream Linux/U-Boot
components, as defined by st,stm32mp15-i2c-non-secure specific
compatible string ID.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: counter: stm32_stgen: add STGEN driver

STGEN is the platform timer. It generates a time-count value that provides
a consistent view of time for multiple processors and other blocks in a
dev

drivers: counter: stm32_stgen: add STGEN driver

STGEN is the platform timer. It generates a time-count value that provides
a consistent view of time for multiple processors and other blocks in a
device. It is physically linked to the ARM generic timer.

Add the STGEN driver that is in charge of configuring the ARM generic
timer source and send an SMC to the BL31 monitor to update the CP15
register. This driver is only compatible for 64bits platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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