| #
7114b0c5 |
| 08-Dec-2022 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
drivers: ele: move ELE to a dedicated directory
Created a new folder in core/drivers/crypto named ele
and moved ele.c in that folder.
This is done for making the base for further crypto driver
based
drivers: ele: move ELE to a dedicated directory
Created a new folder in core/drivers/crypto named ele
and moved ele.c in that folder.
This is done for making the base for further crypto driver
based on ELE.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| #
c7f9abce |
| 21-Nov-2023 |
Xiaoxu Zeng <zengxiaoxu@huawei.com> |
drivers: implement HiSilicon Queue Management (QM) module
The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management
drivers: implement HiSilicon Queue Management (QM) module
The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management module QM is used to interact with software.
Each accelerator module integrates a QM. Software issues tasks to the SQ
(Submmision Queue),and the QM obtains the address of the SQE (Submmision
Queue Element). The BD (Buffer Description, same as SQE) information is
sent to the accelerator. After the task processing is complete, the
accelerator applies for a write-back address from the QM to write back
the SQ.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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|
| #
614bc034 |
| 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: versal: interprocessor communication
Interface to the PLM xilsecure service.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
crypto: versal: interprocessor communication
Interface to the PLM xilsecure service.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| #
e752c173 |
| 11-Feb-2022 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
crypto/aspeed: ast2600: Add HACE HW hash support
Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.
This patch adds
crypto/aspeed: ast2600: Add HACE HW hash support
Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.
This patch adds the driver support for AST2600 HACE to provide
HW-assisted hash for the SHA family. The initial driver structure
for Aspeed crypto engines is also constructed.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
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|
| #
5e64ae67 |
| 26-Jul-2021 |
Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> |
crypto: stm32: use CRYP IP for CIPHER algorithms
Add CRYP IP drivers, and add STM32 CRYP as a drvcrypt cipher provider.
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Reviewed-b
crypto: stm32: use CRYP IP for CIPHER algorithms
Add CRYP IP drivers, and add STM32 CRYP as a drvcrypt cipher provider.
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| #
a3ca687d |
| 24-Sep-2020 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: implement se050 driver
Add AES_CTR/RSA/RNG/HUK support for NXP SE050 via the Plug And Trust
library.
Tested on imx8mm LPDDR EVK and imx6ull EVK.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@
drivers: implement se050 driver
Add AES_CTR/RSA/RNG/HUK support for NXP SE050 via the Plug And Trust
library.
Tested on imx8mm LPDDR EVK and imx6ull EVK.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| #
2d7a8964 |
| 06-Aug-2019 |
Cedric Neveux <cedric.neveux@nxp.com> |
driver: implement CAAM driver
Add the NXP CAAM drivers:
- Random generator (instantiation and random generation)
- Hash
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Etienne Ca
driver: implement CAAM driver
Add the NXP CAAM drivers:
- Random generator (instantiation and random generation)
- Hash
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| #
7222fc6a |
| 06-Aug-2019 |
Cedric Neveux <cedric.neveux@nxp.com> |
core: driver: generic resources for crypto device driver
Add a generic cryptographic driver interface connecting
TEE Crypto generic APIs to HW driver interface
The Generic Crypto Driver interface i
core: driver: generic resources for crypto device driver
Add a generic cryptographic driver interface connecting
TEE Crypto generic APIs to HW driver interface
The Generic Crypto Driver interface in the core/driver/crypto/crypto_api
is implemented to be able to use a HW driver.
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
show more ...
|