| 40e40cd2 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: PM service
Calls the TF-A exported SiP services or PLM PM APIs.
The programming of the FPGA bitstream is being phased out from the TF-A
so it is no longer supported as such: the re
drivers: versal: PM service
Calls the TF-A exported SiP services or PLM PM APIs.
The programming of the FPGA bitstream is being phased out from the TF-A
so it is no longer supported as such: the recommended interface uses
the MBOX driver to the PLM.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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|
| 6301ca1c | 24-Sep-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: se050: updates to the crypto object deletion interface
Keys created on the Secure Element NVM via the PKCS#11 TA are removed
by scanning the data buffer holding the reference to the key duri
crypto: se050: updates to the crypto object deletion interface
Keys created on the Secure Element NVM via the PKCS#11 TA are removed
by scanning the data buffer holding the reference to the key during
the release of the object.
The storage allocated to hold those keys (ECC/RSA) is always below the
page size length which seems like a reasonable figure to use for future
extensions.
- This commit avoids scanning objects larger than that length.
This commit also updates the interface to delegate the actual handling
of the object to the crypto driver instead of passing just the raw data
contained in the object.
The cryptographic layer is also being allowed to block the deletion of
the object. This is to cover the scenario where the I2C device is not
accessible while a reference to the key is being removed from the secure
storage in the filesystem.
Incidentally also fixes regression 6018: this test releases an object
of size 0xA0000 which can't be scanned due to this part of the code
hitting an Out of Memory condition.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 4b46e0e8 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: mailbox communication
Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: J
drivers: versal: mailbox communication
Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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|
| 98fca444 | 29-Aug-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: stm32_i2c: optimize the master receive path
Early error detection prevents an invalid read request made to the
device from blocking the bus for the whole transfer timeout.
Signed-off-by: J
drivers: stm32_i2c: optimize the master receive path
Early error detection prevents an invalid read request made to the
device from blocking the bus for the whole transfer timeout.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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|
| 14b14d5a | 18-Aug-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
se050: glue: i2c_stm32
To add support in the device tree - since the NXP SE05x device node
has not been agreed yet - the user must provide an alias to the bus
where the device is located.
Once the
se050: glue: i2c_stm32
To add support in the device tree - since the NXP SE05x device node
has not been agreed yet - the user must provide an alias to the bus
where the device is located.
Once the SE05X node has been agreed, support will be added to all
OP-TEE supported platforms.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| 646c0a2b | 18-Aug-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: stm32_i2c: fix read operations on I2C_MODE_MASTER mode
One of the valid conditions that leads to the generation of a NACK
is when the controller-receiver signals the end of the transfer
to
drivers: stm32_i2c: fix read operations on I2C_MODE_MASTER mode
One of the valid conditions that leads to the generation of a NACK
is when the controller-receiver signals the end of the transfer
to the target transmitter.
The code being fixed - not clearing the NACK - was causing subsequent
write operations to fail.
This has been validated using the NXP SE050 device.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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|
| 3a340005 | 12-Sep-2022 |
Andrew Mustea <andrew.mustea@microsoft.com> |
core: drivers: nxp: Add LX2160A-series SecMon driver
- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os bui
core: drivers: nxp: Add LX2160A-series SecMon driver
- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os build requires the
CFG_LS_SEC_MON flag.
Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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|
| 4afbdbdd | 01-Aug-2022 |
Anton Eliasson <anton.eliasson@axis.com> |
drivers: scmi-msg: Propagate errors from platform voltd_get_level
plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows erro
drivers: scmi-msg: Propagate errors from platform voltd_get_level
plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows errors from the
platform SCMI server implementation to be propagated to the REE.
The implementation for stm32mp1 is updated to handle at least some
possible errors.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Anton Eliasson <anton.eliasson@axis.com>
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|
| cd495a5a | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: general purpose i/o
Provide access to the GPIO controller on Versal ACAP.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.or
drivers: versal: general purpose i/o
Provide access to the GPIO controller on Versal ACAP.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| c2f16fe3 | 24-Feb-2022 |
Clement Faure <clement.faure@nxp.com> |
core: driver: rework the SC API to make compatible with the new MU driver
Rework the SC API to leverage the common MU driver.
This re-work implies the deletion of duplicate functions that are now
im
core: driver: rework the SC API to make compatible with the new MU driver
Rework the SC API to leverage the common MU driver.
This re-work implies the deletion of duplicate functions that are now
implemented in the MU driver instead
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 9756bcc4 | 24-Feb-2022 |
Clement Faure <clement.faure@nxp.com> |
core: driver: add common i.MX MU driver
Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.
This driver includes a generic part and
core: driver: add common i.MX MU driver
Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.
This driver includes a generic part and an hardware abstraction layer
for low level MU functions.
The MU driver implements the HAL for the following platforms:
- mx8ulpevk
- mx8qmmek/imx8qxpmek
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 830dc5c6 | 29-Aug-2022 |
Gerard Koskamp <gerard.koskamp@nedap.com> |
drivers: imx-i2c: add support for imx8mn
Add i2c support for imx8mn platforms
Signed-off-by: Gerard Koskamp <gerard.koskamp@nedap.com>
Reviewed-by: Robert Krikke <robert.krikke@nedap.com>
Acked-by:
drivers: imx-i2c: add support for imx8mn
Add i2c support for imx8mn platforms
Signed-off-by: Gerard Koskamp <gerard.koskamp@nedap.com>
Reviewed-by: Robert Krikke <robert.krikke@nedap.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
show more ...
|
| 39008932 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto_api: acipher: correct ECC NIST-P521 key size
NIST P521 uses 521-bit private keys.
This change might impact platforms that expect a certain alignment
on the key size (i.e. CAAM)
Signed-off-b
crypto_api: acipher: correct ECC NIST-P521 key size
NIST P521 uses 521-bit private keys.
This change might impact platforms that expect a certain alignment
on the key size (i.e. CAAM)
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| ac3facb9 | 29-Aug-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: caam: ecc: key size must be a multiple of 8
Enforce the alignment required by the CAAM hardware.
Notice that the NIST-P521 curve uses a 521 bit private key
hence why this change is needed.
drivers: caam: ecc: key size must be a multiple of 8
Enforce the alignment required by the CAAM hardware.
Notice that the NIST-P521 curve uses a 521 bit private key
hence why this change is needed.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| c0e8ad83 | 22-Aug-2022 |
Jose Quaresma <jose.quaresma@foundries.io> |
drivers: imx: dcp: fix compilation address error
hwkey->data will never be null because it is an array
struct tee_hw_unique_key {
uint8_t data[HW_UNIQUE_KEY_LENGTH];
};
Fix the following w
drivers: imx: dcp: fix compilation address error
hwkey->data will never be null because it is an array
struct tee_hw_unique_key {
uint8_t data[HW_UNIQUE_KEY_LENGTH];
};
Fix the following with gcc12:
| core/drivers/imx/dcp/dcp_huk.c: In function 'tee_otp_get_hw_unique_key':
| core/drivers/imx/dcp/dcp_huk.c:71:23: error: the comparison will always evaluate as 'true' for the address of 'data' will never be NULL [-Werror=address]
| 71 | if (!hwkey || !hwkey->data) {
| | ^
Signed-off-by: Jose Quaresma <jose.quaresma@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>
show more ...
|
| e3c7f166 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto-api: rsassa: pass algorithm to implementation
This is required for drivers that might only support some of the
algorithms.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: J
crypto-api: rsassa: pass algorithm to implementation
This is required for drivers that might only support some of the
algorithms.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>
show more ...
|
| dfeed924 | 07-May-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_huk: Add AES eFuse and HUK seed support
When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption
drivers: zynqmp_huk: Add AES eFuse and HUK seed support
When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption is
in use AES eFuse key becomes device key instead of PUF generated key.
In order to re-plenish additional device specific entropy that PUF would
provide utilize selected set of User programmable eFuses.
Selected user eFuses should be programmed during device manufacturing with
cryptographically good random numbers.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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|
| 214ee971 | 27-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zymqmp_pm: add USER eFuse support
Adds necessary defines for accessing USER eFuses.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.car
drivers: zymqmp_pm: add USER eFuse support
Adds necessary defines for accessing USER eFuses.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 6e96536e | 30-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_pm: Add eFuse programming support
Add support to program eFuses utiling functionality found in PMU firmware.
If eFuse programming functionality has been disabled in PMU firmware the
drivers: zynqmp_pm: Add eFuse programming support
Add support to program eFuses utiling functionality found in PMU firmware.
If eFuse programming functionality has been disabled in PMU firmware then
programming will fail.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 97558570 | 29-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_pm: fix cache alignment for eFuse operation
Allocate cache aligned temporary memory for both eFuse operation request
and data buffer to make sure that operation is always cache align
drivers: zynqmp_pm: fix cache alignment for eFuse operation
Allocate cache aligned temporary memory for both eFuse operation request
and data buffer to make sure that operation is always cache aligned and to
make usage easier.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 8e155bae | 30-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
imx: dcp: switch to new alloc_cache_aligned()
Use commonized outer cache line aligned memory allocator instead of having
local implementation.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@va
imx: dcp: switch to new alloc_cache_aligned()
Use commonized outer cache line aligned memory allocator instead of having
local implementation.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 613c6309 | 13-Aug-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: se050: optional I2C access via trampoline
Platforms with secure I2C buses (i.e: STM32MP1) or those with only
a secure element on the bus might prefer not to delegate the I2C
traffic to the
drivers: se050: optional I2C access via trampoline
Platforms with secure I2C buses (i.e: STM32MP1) or those with only
a secure element on the bus might prefer not to delegate the I2C
traffic to the REE.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| 961785fb | 29-Jul-2022 |
Tim Anderson <tim.anderson@foundries.io> |
drivers: imx_i2c: update the daisy chain setting for I2C1
Looking at IMX6ULLRM Rev. 1, 11/2017 paragraph 32.6.329
says the daisy chain for SDA on I2C1 on imx6ull-evk is 2 not 1.
Signed-off-by: Tim
drivers: imx_i2c: update the daisy chain setting for I2C1
Looking at IMX6ULLRM Rev. 1, 11/2017 paragraph 32.6.329
says the daisy chain for SDA on I2C1 on imx6ull-evk is 2 not 1.
Signed-off-by: Tim Anderson <tim.anderson@foundries.io>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
show more ...
|
| 460dc361 | 29-Jul-2022 |
Tim Anderson <tim.anderson@foundries.io> |
drivers: imx_i2c: update the I2C initialization
NXP drivers in both u-boot and linux waits 50us after enabling
the bus controller to stabilize the bus.
Signed-off-by: Tim Anderson <tim.anderson@fou
drivers: imx_i2c: update the I2C initialization
NXP drivers in both u-boot and linux waits 50us after enabling
the bus controller to stabilize the bus.
Signed-off-by: Tim Anderson <tim.anderson@foundries.io>
Acked-by: Clement Faure <clement.faure@nxp.com>
show more ...
|
| 48ca91ed | 31-Mar-2021 |
Vahid Dukandar <vahidd@microsoft.com> |
drivers: bcm_sotp: add sotp write support
- Added write support for bcm secure one time programmable fuses.
- bcm_iproc_sotp_mem_read() now takes in a bool value for sotp_add_ecc
instead of an int
drivers: bcm_sotp: add sotp write support
- Added write support for bcm secure one time programmable fuses.
- bcm_iproc_sotp_mem_read() now takes in a bool value for sotp_add_ecc
instead of an int to denote if error checking memory is supported.
- Updated debug and error messages to return TEE_result codes.
Signed-off-by: Vahid Dukandar <vahidd@microsoft.com>
Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|