drivers: crypto: hisilicon: add DH algorithm

add operation of DH algorithm, including alloc_keypair,
gen_keypair and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Etienne Car

drivers: crypto: hisilicon: add DH algorithm

add operation of DH algorithm, including alloc_keypair,
gen_keypair and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: Add RISC-V Zkr hardware random number generator support

The RISC-V Zkr entropy source extension introduces a physical
entropy source compliant with NIST SP 800-90B or BSI AIS-31
standards v

drivers: Add RISC-V Zkr hardware random number generator support

The RISC-V Zkr entropy source extension introduces a physical
entropy source compliant with NIST SP 800-90B or BSI AIS-31
standards via the seed CSR.

Note that this driver cannot be used unless access is explicitly
granted by M-mode, e.g. OpenSBI have to set mseccfg.SSEED for
OP-TEE OS.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: add IPCC driver and its RIF support

This driver implements RIF configuration for IPCC, which is a RIF
aware IP. It means that the IPCC driver is in charge of configuring its
own RIF restric

drivers: add IPCC driver and its RIF support

This driver implements RIF configuration for IPCC, which is a RIF
aware IP. It means that the IPCC driver is in charge of configuring its
own RIF restrictions and that the IPCC has dedicated RIF configuration
registers.

RIF configuration data is part of the ipcc_pdata structure.

CID filtering is applied to the entirety of the channels of a processor.
When CID filtering is enabled for a processor, it enables the filtering and
the IPCC interrupt routing for all of its IPCC channels.

However, security and privilege configuration granularity go as far as
configuration for each IPCC channel.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add RIF support driver for HSEM

This driver implements RIF configuration for HSEM, which is a RIF
aware IP. It means that the HSEM driver is in charge of configuring its
own RIF restriction

drivers: add RIF support driver for HSEM

This driver implements RIF configuration for HSEM, which is a RIF
aware IP. It means that the HSEM driver is in charge of configuring its
own RIF restrictions and that the HSEM has dedicated RIF configuration
registers.

HSEM has two types of CID filtering registers.
-For processor filtering : HSEM_CnCIDCFGR
When CFEN is enabled: processor[n] CID filtering enabled for HSEM_(S)CnIER,
HSEM_(S)CnICR, HSEM_(S)CnISR, and HSEM_(S)CnMISR registers and for allowed
list filter usage in HSEM_GpCIDCFGR.SEM_WLIST_Cn. The CID is put in the
CID bitfield.

-For semaphore group filtering : HSEM_GpCIDCFGR
Used to apply CID filtering over a group of semaphore. The same policy
applies to all semaphores present in the group. This register handles
what are the processor's CID who are white-listed for the group in the
SEM_WLIST_C bitfield.

Therefore, both these registers are interconnected.

Security and privilege configuration granularity expands to each individual
semaphore.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add HPDMA driver with RIF support

This driver implements RIF configuration for HPDMA, which is a RIF aware
IP. It means that the HPDMA driver is in charge of configuring its own RIF
restric

drivers: add HPDMA driver with RIF support

This driver implements RIF configuration for HPDMA, which is a RIF aware
IP. It means that the HPDMA driver is in charge of configuring its own RIF
restrictions and that the HPDMA has dedicated RIF configuration registers.

RIF configuration is possible when the executing context is TDCID.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add FMC driver with RIF support

This driver implements RIF configuration for FMC, which is a RIF aware IP.
It means that the FMC driver is in charge of configuring its own RIF
restrictions

drivers: add FMC driver with RIF support

This driver implements RIF configuration for FMC, which is a RIF aware IP.
It means that the FMC driver is in charge of configuring its own RIF
restrictions and that the FMC has dedicated RIF configuration registers.

Additional check on RIF configuration is added for this IP when debug is
on.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: firewall: move RIFPROT binding

Move RIFPROT macro definition in stm32mp25-rif.h as it is common
to all RIF-based peripherals.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.s

dt-bindings: firewall: move RIFPROT binding

Move RIFPROT macro definition in stm32mp25-rif.h as it is common
to all RIF-based peripherals.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile

plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile for sama7g5 OP-TEE support.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed

plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: update "#include" list of the header files

Remove the unused header files from "#include".
"#include" the header files needed explicitly even if they are included
indirectly.

Si

drivers: atmel_wdt: update "#include" list of the header files

Remove the unused header files from "#include".
"#include" the header files needed explicitly even if they are included
indirectly.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: remove the unused variable from "struct atmel_wdt"

The variable "unsigned long rate" is not used, remove it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fo

drivers: atmel_wdt: remove the unused variable from "struct atmel_wdt"

The variable "unsigned long rate" is not used, remove it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_wdt: upgrade to support sama7g5 watchdog

In sama7g5 there's a DWDT (Dual Watchdog Timer) and the registers
are not the same as the wdt for sama5d2. Here the DWD is handled
as 2 watchd

drivers: atmel_wdt: upgrade to support sama7g5 watchdog

In sama7g5 there's a DWDT (Dual Watchdog Timer) and the registers
are not the same as the wdt for sama5d2. Here the DWD is handled
as 2 watchdogs.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_i2c: protect bus access with a mutex

Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by:

drivers: stm32_i2c: protect bus access with a mutex

Protect concurrent accesses to an STM32 I2C bus with a PM aware mutex.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: stm32_rifsc: remove use of CFG_PM

Remove use of CFG_PM from STM32 RIFSC driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien

drivers: firewall: stm32_rifsc: remove use of CFG_PM

Remove use of CFG_PM from STM32 RIFSC driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: remove use of CFG_PM

Remove use of CFG_PM from STM32 RNG driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@fo

drivers: stm32_rng: remove use of CFG_PM

Remove use of CFG_PM from STM32 RNG driver since this configuration
switch is not defined in OP-TEE OS.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_cryp: add pm to CRYP driver

Add power management support to the CRYP driver through suspend/resume
callbacks.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Sig

drivers: crypto: stm32_cryp: add pm to CRYP driver

Add power management support to the CRYP driver through suspend/resume
callbacks.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_cryp: add delay when resetting CRYP peripheral.

Add 2 us of delay between reset assert and reset deassert to ensure the
peripheral is properly reset.

Signed-off-by: Thomas Bo

drivers: crypto: stm32_cryp: add delay when resetting CRYP peripheral.

Add 2 us of delay between reset assert and reset deassert to ensure the
peripheral is properly reset.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_cryp: remove reset binding requirements

Remove panic during probe when "resets" property is not found because
it's optional in most cases.

Signed-off-by: Thomas Bourgoin <tho

drivers: crypto: stm32_cryp: remove reset binding requirements

Remove panic during probe when "resets" property is not found because
it's optional in most cases.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: hisilicon: init HPRE hardware block

The HiSilicon HPRE is a High Performance RSA Engine.
This module implement the hardware initialization of
the HPRE.

Signed-off-by: loubaihui <lo

drivers: crypto: hisilicon: init HPRE hardware block

The HiSilicon HPRE is a High Performance RSA Engine.
This module implement the hardware initialization of
the HPRE.

Signed-off-by: loubaihui <loubaihui1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: regulator: use mutex_pm_aware

Use newly introduced struct mutex_pm_aware semaphore to protect
regulator accesses.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Eti

drivers: regulator: use mutex_pm_aware

Use newly introduced struct mutex_pm_aware semaphore to protect
regulator accesses.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: replace clock main spinlock with a mutex

Change clock framework lock from an interrupts masked spinning lock
to a mutex. This allows the clock framework to better handle slow
stabilizi

drivers: clk: replace clock main spinlock with a mutex

Change clock framework lock from an interrupts masked spinning lock
to a mutex. This allows the clock framework to better handle slow
stabilizing clocks as PLLs without masking the system interrupt
which can have side effects on the REE or even the TEE.

To support clock accesses during low power state transition sequences
while non-secure world is no operating, the lock is not taken when
the execution is not in the scope of a TEE thread.

This change is not expected to impact supported platforms that currently
only access clock operation from thread contexts or atomic PM sequences.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: replace REGISTER_TIME_SOURCE()

Remove REGISTER_TIME_SOURCE() and implement tee_time_get_sys_time() and
tee_time_get_sys_time_protection_level() directly in the file where
REGISTER_TIME_SOURCE(

core: replace REGISTER_TIME_SOURCE()

Remove REGISTER_TIME_SOURCE() and implement tee_time_get_sys_time() and
tee_time_get_sys_time_protection_level() directly in the file where
REGISTER_TIME_SOURCE() was used previously.

By avoiding indirect calls the linker can optimize the dependency tree
properly and we can remove the DECLARE_KEEP_PAGER() directive needed for
arm_cntpct_time_source.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: clk-stm32mp13: fix memory corruption on oscillator parent

Fix oscillators struct clk instances for STM32MP13 clock driver. These
clocks have 1 parent that is set during driver initiali

drivers: clk: clk-stm32mp13: fix memory corruption on oscillator parent

Fix oscillators struct clk instances for STM32MP13 clock driver. These
clocks have 1 parent that is set during driver initialization, based on
device tree content, whereas referred bugged commit defined 0 parents
and did not allocate memory for the parent reference.

Fixes: 95f2142bf848 ("drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired")
Tested-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator leve

drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator level value depends on the parent regulator
(supply). It is up the regulator drivers to cache or not this
value in their private data if applicable.

Fixes: 1a3d3273040b ("drivers: regulator framework")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ac

drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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