arm: aspeed: Update secure memory layout

Update the TZDRAM region based on the 1GB DRAM space of
Aspeed AST2600/AST2700 EVBs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Je

arm: aspeed: Update secure memory layout

Update the TZDRAM region based on the 1GB DRAM space of
Aspeed AST2600/AST2700 EVBs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
inclu

riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
include path of RISC-V PLIC driver header is fixed.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Load register TP from thread_user_mode_rec in trap handler

RISC-V kernel uses TP register to store thread_core_local structure.
When the thread enters user mode, the value of TP is used

core: riscv: Load register TP from thread_user_mode_rec in trap handler

RISC-V kernel uses TP register to store thread_core_local structure.
When the thread enters user mode, the value of TP is used by user mode.
Therefore, when CPU enters trap handler, it needs to restore TP to get
thread_core_local structure. In previous implementation, the value of TP
is saved under kernel SP before entering user mode, and the trap handler
restores TP from that stack location. However, the value of TP has
already been saved into the thread_user_mode_rec structure, which is
also upon kernel SP, before entering user mode. So the value of TP can
be restored just from thread_user_mode_rec, instead of saving into
another location which is under the kernel SP.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Support Privileged Access Never by CSR status.SUM bit

The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When

core: riscv: Support Privileged Access Never by CSR status.SUM bit

The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When SUM bit is
0, S-mode accesses to pages whose U bit of corresponding PTE is set will
fault. When SUM bit is 1, these accesses are permitted.

When CFG_PAN is disabled in RISC-V architecture, the status.SUM bit is
initialized as 1 by default. Therefore all accesses to user pages will
succeed. When CFG_PAN is enabled, the status.SUM bit is initialized as
0, and only set to 1 when kernel needs to access user pages.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Fix thread_rpc() wrong stack usage and CSR value

Since there are four registers to be stored onto stack, we should
preserve up to 32 bytes space on the stack instead of only 16 bytes,
o

core: riscv: Fix thread_rpc() wrong stack usage and CSR value

Since there are four registers to be stored onto stack, we should
preserve up to 32 bytes space on the stack instead of only 16 bytes,
otherwise the stack overflow occurs. The s0 is regarded as frame
pointer. The value of CSR status is also restored before returning from
thread_rpc().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Fix width of status CSR

Since we also support RV64 with 64-bit register width, fix the width of
status CSR by declaring it as "unsigned long" and encoding it by general
bit-wise operati

core: riscv: Fix width of status CSR

Since we also support RV64 with 64-bit register width, fix the width of
status CSR by declaring it as "unsigned long" and encoding it by general
bit-wise operations instead of invoking fixed-width API.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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plat-marvell: Add support for CN10K SoCs

Add support for CN10K SoCs from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-cn10ka
2. Pass

plat-marvell: Add support for CN10K SoCs

Add support for CN10K SoCs from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-cn10ka
2. Passed xtest

Signed-off-by: Gowthami <gthiagarajan@marvell.com>
Reviewed-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: support larger values for CFG_TEE_CORE_NB_CORE

With larger values of CFG_TEE_CORE_NB_CORE (for example, 18 on the
marvell-cnf10ka platform) CORE_MMU_BASE_TABLE_OFFSET becomes to large to
be us

core: support larger values for CFG_TEE_CORE_NB_CORE

With larger values of CFG_TEE_CORE_NB_CORE (for example, 18 on the
marvell-cnf10ka platform) CORE_MMU_BASE_TABLE_OFFSET becomes to large to
be used as an immediate value in add and sub assembly instructions. This
is handle by using the new add_imm and sub_imm macros where needed. But
the add_imm and sub_imm macros can't handle complex defines so
CORE_MMU_BASE_TABLE_OFFSET must be evaluated in asm-defines.c first.

This should fix errors like:
core/arch/arm/kernel/thread_a64.S: Assembler messages:
core/arch/arm/kernel/thread_a64.S:339: Error: immediate out of range
core/arch/arm/kernel/thread_a64.S:347: Error: immediate out of range
core/arch/arm/kernel/thread_a64.S:355: Error: immediate out of range
core/arch/arm/kernel/thread_a64.S:372: Error: immediate out of range
core/arch/arm/kernel/thread_a64.S:379: Error: immediate out of range
core/arch/arm/kernel/thread_a64.S:386: Error: immediate out of range
core/arch/arm/kernel/thread_a64.S:660: Error: immediate out of range
core/arch/arm/kernel/thread_a64.S:732: Error: immediate out of range
make: *** [mk/compile.mk:165: out/core/arch/arm/kernel/thread_a64.o] Error 1

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Gowthami <gthiagarajan@marvell.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: add add_imm and sub_imm assembly macros

Adds the add_imm and sub_imm assembly macros capable of adding or
subtracting a 24-bit immediate value to or from a general purpose
register.

Si

core: arm64: add add_imm and sub_imm assembly macros

Adds the add_imm and sub_imm assembly macros capable of adding or
subtracting a 24-bit immediate value to or from a general purpose
register.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: riscv.mk: define CFG_WITH_LPAE

Set CFG_WITH_LPAE according to CFG_CORE_LARGE_PHYS_ADDR.
Memory manager makes use of CFG_WITH_LPAE, therefore, we set it
according to the platform specifi

core: riscv: riscv.mk: define CFG_WITH_LPAE

Set CFG_WITH_LPAE according to CFG_CORE_LARGE_PHYS_ADDR.
Memory manager makes use of CFG_WITH_LPAE, therefore, we set it
according to the platform specifications.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: mm: move pgt_cache.c to core/mm

This commit moves core/arch/arm/mm/pgt_cache.c to core/mm/pgt_cache.c
The implementation can be used by other architectures.
The commit does not rename CFG_CORE

core: mm: move pgt_cache.c to core/mm

This commit moves core/arch/arm/mm/pgt_cache.c to core/mm/pgt_cache.c
The implementation can be used by other architectures.
The commit does not rename CFG_CORE_PREALLOC_EL0_TBLS flag and other
depending flags (CFG_WITH_PAGER, CFG_WITH_LPAE). Therefore, an
architecture implementation may set or not these flags.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: asan: arm64: increase stack sizes for ASAN

Increase STACK_TMP_SIZE and STACK_THREAD_SIZE when
CFG_CORE_SANITIZE_KADDRESS=y. With that, xtest passes on
PLATFORM=vexpress-qemu_armv8a.

Signed-of

core: asan: arm64: increase stack sizes for ASAN

Increase STACK_TMP_SIZE and STACK_THREAD_SIZE when
CFG_CORE_SANITIZE_KADDRESS=y. With that, xtest passes on
PLATFORM=vexpress-qemu_armv8a.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: asan: initialize __exidx and __extab only for __arm__

__exidx_start/__exidx_end and __extab_start/__extab_end are defined
only for 32-bit Arm, so guard their ASAN initialization with __arm__.

core: asan: initialize __exidx and __extab only for __arm__

__exidx_start/__exidx_end and __extab_start/__extab_end are defined
only for 32-bit Arm, so guard their ASAN initialization with __arm__.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu_armv8a: define CFG_ASAN_SHADOW_OFFSET

Sets the proper value for CFG_ASAN_SHADOW_OFFSET in order to enable
CFG_CORE_SANITIZE_KADDRESS=y.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro

qemu_armv8a: define CFG_ASAN_SHADOW_OFFSET

Sets the proper value for CFG_ASAN_SHADOW_OFFSET in order to enable
CFG_CORE_SANITIZE_KADDRESS=y.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: plat-versal: Add maybe_unused attribute to constant strings

If log level is set to print only EMSGs, constant strings can be unused.
Add maybe_unused attribute to prevent compilation erro

core: arm: plat-versal: Add maybe_unused attribute to constant strings

If log level is set to print only EMSGs, constant strings can be unused.
Add maybe_unused attribute to prevent compilation errors.

Signed-off-by: Sriram Sriram <sriramsriram@microsoft.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: conf: default enable SAES

Default enable SAES compilation.
Enable the STM32_CRYPTO_DRIVERS if any crypto SAES or CRYP is compiled.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@fos

plat-stm32mp1: conf: default enable SAES

Default enable SAES compilation.
Enable the STM32_CRYPTO_DRIVERS if any crypto SAES or CRYP is compiled.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: allocate SAES to secure world

SAES was allocated to non-secure world but it should be allocated to
OP-TEE.

Fixes: b5ec47ff7668 ("plat-stm32mp1: temporary ETZPC configuration")
Signed

plat-stm32mp1: allocate SAES to secure world

SAES was allocated to non-secure world but it should be allocated to
OP-TEE.

Fixes: b5ec47ff7668 ("plat-stm32mp1: temporary ETZPC configuration")
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-nuvoton: force CFG_EXTERNAL_DT=n

Disables DT insecure warning

Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>

plat-nuvoton: force CFG_EXTERNAL_DT=n

Disables DT insecure warning

Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-nuvoton: add HUK reading

Implements HUK reading from DME PCR0 located in the PCI mailbox

Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Hila Miranda-Kuzi <hil

plat-nuvoton: add HUK reading

Implements HUK reading from DME PCR0 located in the PCI mailbox

Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-nuvoton: change load address, shared memory and SDP memory

Changes load address of OPTEE-OS from 0x36000000 to 0x02100000
Moves shared memory to 0x06000000
Moves SDP memory to 0x05F00000

Co-de

plat-nuvoton: change load address, shared memory and SDP memory

Changes load address of OPTEE-OS from 0x36000000 to 0x02100000
Moves shared memory to 0x06000000
Moves SDP memory to 0x05F00000

Co-developed-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: plat-ls: Add CFG_WITH_ARM_TRUSTED_FW flag

If using ARM Trusted Firmware-A, then the GIC initialization is done in
BL31.

Fixes: 2b9f23923175 ("plat-ls: Add support for armv8 platform flav

core: arm: plat-ls: Add CFG_WITH_ARM_TRUSTED_FW flag

If using ARM Trusted Firmware-A, then the GIC initialization is done in
BL31.

Fixes: 2b9f23923175 ("plat-ls: Add support for armv8 platform flavours")
Signed-off-by: Carl Lamb <calamb@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: arm: plat-bcm: Force CFG_CORE_ARM64_PA_BITS=48

Set CFG_CORE_ARM64_PA_BITS in Broadcom platform file. This fixes a crash
when setting up memory addresses on the Broadcom stingray NS3 platform.

core: arm: plat-bcm: Force CFG_CORE_ARM64_PA_BITS=48

Set CFG_CORE_ARM64_PA_BITS in Broadcom platform file. This fixes a crash
when setting up memory addresses on the Broadcom stingray NS3 platform.

Signed-off-by: Stephen Carlson <stcarlso@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: preserve PSTATE.PAN when making SPSR

When setup_unwind_user_mode() prepares to resume execution after
syscall_sys_return() or when a thread is suspended a new SPSR is
fabricated base on

core: arm64: preserve PSTATE.PAN when making SPSR

When setup_unwind_user_mode() prepares to resume execution after
syscall_sys_return() or when a thread is suspended a new SPSR is
fabricated base on the current PSTATE.

Until now when remaining in S-EL1 to fabricate an SPSR only the
PSTATE.DAIF bits had to be taken into account. However, with PSTATE.PAN
there's yet another bit to consider. Since PSTATE has a few more bits
and more may be added as AArch64 evolves this problem is only going to
get worse. So implement this in a single internal C function to replace
current open codes C and assembly versions.

The AArch64 assembly versions of thread_rpc() are renamed to
thread_rpc_spsr() to indicate that SPSR is passed in the second argument
instead of having it open coded internally in the assembly function.

New C wrapper functions are added to preserve the old thread_rpc()
interface as needed.

handle_user_mode_panic() is still basing its created SPSR on the saved
SPSR from S-EL0, but now PAN bit is copied too.

Fixes: 6fa59c9a70dc ("arm64: Introduce permissive PAN implementation")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: add feat_pan_implemented()

Adds the helper function feat_pan_implemented() to extract the
implemented PAN version. No version is 0 so this function can be used
tested as a boolean too.

S

core: arm: add feat_pan_implemented()

Adds the helper function feat_pan_implemented() to extract the
implemented PAN version. No version is 0 so this function can be used
tested as a boolean too.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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arm64: add read_pan() and SPSR_64_PAN

Adds the wrapper function read_pan() to read PSTATE.PAN, also adds a
SPSR_64_PAN define.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

arm64: add read_pan() and SPSR_64_PAN

Adds the wrapper function read_pan() to read PSTATE.PAN, also adds a
SPSR_64_PAN define.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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