core: riscv: Apply exception return to handle_user_mode_panic()

Now thread_exit_user_mode() executes exception return to kernel mode.
Invoke xstatus_for_xret() helper function to prepare CSR STATUS

core: riscv: Apply exception return to handle_user_mode_panic()

Now thread_exit_user_mode() executes exception return to kernel mode.
Invoke xstatus_for_xret() helper function to prepare CSR STATUS for
exception return.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Refine thread trap handler

In order to support SMP, we made change on CSR SCRATCH from kernel stack
pointer to be kernel TP(thread_core_local). So that we can get TP from
SCRATCH easily

core: riscv: Refine thread trap handler

In order to support SMP, we made change on CSR SCRATCH from kernel stack
pointer to be kernel TP(thread_core_local). So that we can get TP from
SCRATCH easily in trap handler when the thread is in user mode. We also
save/restore CSR IE, kernel GP and SP so that we can handle task
migration to another hart.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Refine thread enter/exit user mode

Now when thread is in user mode, the kernel TP is saved into CSR SCRATCH
instead of into kernel stack. The IE is also considered since it
contains mas

core: riscv: Refine thread enter/exit user mode

Now when thread is in user mode, the kernel TP is saved into CSR SCRATCH
instead of into kernel stack. The IE is also considered since it
contains masks of different exceptions.

Apply exception return to thread_exit_user_mode() to let hart correctly
back to kernel mode from exception.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Apply exception return to resume thread

In current implementation, the thread is resumed by function return. It
is not suitable for all scenarios, especially when the thread should be
r

core: riscv: Apply exception return to resume thread

In current implementation, the thread is resumed by function return. It
is not suitable for all scenarios, especially when the thread should be
resumed to user mode. The kernel mode can not return to user mode by
pure function return.

This commit applies exception return to resume the thread. The EPC and
IE are added into thread context. The xstatus_for_xret() helper function
is added to prepare the value of CSR STATUS for exception return.
Currently we only consider PIE(previous interrupt-enable) and
PP(previous privilege mode) for exception return.

We clear thread context when the context is reinitialized, enable native
interrupt, and setup kernel GP/TP. The thread_resume() now takes care of
restoring CSR EPC, STATUS, IE, SCRATCH and all general-purpose
registers. Finally it executes exception return to target privilege mode
encoded in CSR STATUS. The registers GP and TP are also restored since
user mode may use them.

This commit also modify the usage of CSR SCRATCH. In current
implementation the SCRATCH is used to save kernel stack pointer when the
thread is in user mode. The value of TP, which stores thread_core_local
structure, is saved into kernel stack before entering user mode. The
trap handler can then get TP(thread_core_local) from kernel stack. This
is not suitable for SMP system, since the thread might be resumed to
another core, and that core gets wrong TP from kernel stack. Fix it by
directly storing TP into CSR SCRATCH.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: boot: fix memtag init sequence

Based on following observations on FVP:
With boot_init_memtag called before MMU enable, DC GZA hits an alignment
fault. This is because all accesses are of devic

core: boot: fix memtag init sequence

Based on following observations on FVP:
With boot_init_memtag called before MMU enable, DC GZA hits an alignment
fault. This is because all accesses are of device type when MMU is off.
Arm ARM states for DC GZA: "If the memory region being modified is any
type of Device memory, this instruction can give an alignment fault."
Moving boot_init_memtag after MMU enable, DC GZA hits a permission
fault, this is because the range returned by core_mmu_get_secure_memory
consists of pages mapped RO (text sections) and then RW (data sections)
consecutively. DC GZA is a write instruction executed towards an RO page
leading to a fault.

To fix this, split boot_init_memtag into two halves:
- Setup memtag operations before MMU is enabled such that MAIR_EL1 is
properly configured for normal tagged memory.
- Clear core TEE RW sections after MMU is enabled.

Closes: https://github.com/OP-TEE/optee_os/issues/6649
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
[jw rewrote boot_clear_memtag()]
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@lina

core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add missing DECLARE_KEEP_PAGER()

Adds missing DECLARE_KEEP_PAGER() for timer_desc, timer_itr_cb(),
arm_cntpct_time_source, wd_ndrv_atomic_cb(), and periodic_callback().
All possibly accessed f

core: add missing DECLARE_KEEP_PAGER()

Adds missing DECLARE_KEEP_PAGER() for timer_desc, timer_itr_cb(),
arm_cntpct_time_source, wd_ndrv_atomic_cb(), and periodic_callback().
All possibly accessed from an interrupt handler and must not be paged.

Fixes: cf707bd0d695 ("core: add callout service")
Fixes: 5b7afacfba96 ("core: arm64: implement timer_init_callout_service()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-synquacer: use cpu_spin_lock_xsave() and friend

Change RNG PTA implementation for synquacer platform to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead
of call

plat-synquacer: use cpu_spin_lock_xsave() and friend

Change RNG PTA implementation for synquacer platform to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead
of calling thread_mask_exceptions()/cpu_spin_lock() pair and
thread_set_exceptions()/cpu_spin_unlock() pair. This makes the
implementation more consistent.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: mm: use thread_unmask_exceptions() where applicable

Change cache_op_outer() to use thread_unmask_exceptions() instead
of thread_set_exceptions() as the function unmasks interruptions it
p

core: arm: mm: use thread_unmask_exceptions() where applicable

Change cache_op_outer() to use thread_unmask_exceptions() instead
of thread_set_exceptions() as the function unmasks interruptions it
previously masked with thread_set_exceptions(). This change makes the
implementation more consistent.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: use cpu_spin_lock_xsave() in generic timer implementation

Change generic timer driver for Arm 64bit architecture to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore

core: arm: use cpu_spin_lock_xsave() in generic timer implementation

Change generic timer driver for Arm 64bit architecture to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore()
instead of calling thread_mask_exceptions()/cpu_spin_lock() pair
and thread_set_exceptions()/cpu_spin_unlock() pair. This makes
the implementation more consistent with the rest of the source tree.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome

plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service usi

plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service using that interrupt ID.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: implement timer_init_callout_service()

Implement timer_init_callout_service() needed to initialize and drive
the callout service. Only available in AArch64.

Signed-off-by: Jens Wikland

core: arm64: implement timer_init_callout_service()

Implement timer_init_callout_service() needed to initialize and drive
the callout service. Only available in AArch64.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: add {read,write}_cntps_cval()

Add read_cntps_cval() and write_cntps_cval() to access CNTPS_CVAL_EL1,
Counter-timer Physical Secure Timer CompareValue register.

Signed-off-by: Jens Wikl

core: arm64: add {read,write}_cntps_cval()

Add read_cntps_cval() and write_cntps_cval() to access CNTPS_CVAL_EL1,
Counter-timer Physical Secure Timer CompareValue register.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-synquacer: add initialization value to local variables

Add missing initialization value to local variables in synquacer
platform RNG driver to better comply with OP-TEE OS coding style
and prev

plat-synquacer: add initialization value to local variables

Add missing initialization value to local variables in synquacer
platform RNG driver to better comply with OP-TEE OS coding style
and prevent developers from being confused when using this example
as a example.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architec

core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architecture or platform only need to implement timer tick count
read function delay_cnt_read() and timer tick frequency (in Hertz)
delay_cnt_freq() which is related to CFG_CORE_HAS_GENERIC_TIMER support.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMER

Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture
since the current implementation provides the necessary routines
in delay

core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMER

Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture
since the current implementation provides the necessary routines
in delay_arch.h outside any configuration switch directive. This change
clarifies riscv based platforms configuration that previously depended
on CFG_CORE_HAS_GENERIC_TIMER default enabling from mk/config.mk.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/m

plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/main.c
doesn't make sense and needs to be disabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: implement __do_semihosting() for Aarch64

Implement __do_semihosting() as documented in the "Semihosting for
Aarch32 and Aarch64" specification [1].

Link: https://github.com/ARM-softwar

core: arm64: implement __do_semihosting() for Aarch64

Implement __do_semihosting() as documented in the "Semihosting for
Aarch32 and Aarch64" specification [1].

Link: https://github.com/ARM-software/abi-aa/blob/2023Q3/semihosting/semihosting.rst [1]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: enable TZC380 driver for all i.mx8m socs

This enables the TrustZone Address Space Controller (TZ380) driver for
all members of the i.MX8M soc family. Enabling the driver ensures
protectio

core: imx: enable TZC380 driver for all i.mx8m socs

This enables the TrustZone Address Space Controller (TZ380) driver for
all members of the i.MX8M soc family. Enabling the driver ensures
protection of the OP-TEE memory regions, so that only the secure world
can access it.

Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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riscv: sbi_console: prefer SBI v2.0 DBCN ecall over legacy sbi_console_putchar()

As the legacy sbi_console_putchar() may be deprecated in the future,
it is recommended to use sbi_dbcn_write_byte() p

riscv: sbi_console: prefer SBI v2.0 DBCN ecall over legacy sbi_console_putchar()

As the legacy sbi_console_putchar() may be deprecated in the future,
it is recommended to use sbi_dbcn_write_byte() provided by SBI v2.0
DBCN extension [1]. However, if the DBCN extension is not supported,
sbi_console_putchar() can still be used as the last resort.

Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/v2.0/src/ext-debug-console.adoc#function-console-write-byte-fid-2 [1]
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: remove unused sbi_console_flush()

sbi_console_flush() won't be implemented, remove the empty function.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Al

riscv: sbi_console: remove unused sbi_console_flush()

sbi_console_flush() won't be implemented, remove the empty function.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: remove global spinlock

sbi_console_putc() has been protected by puts_lock, so
remove the superfluous spinlock.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewe

riscv: sbi_console: remove global spinlock

sbi_console_putc() has been protected by puts_lock, so
remove the superfluous spinlock.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: remove unneeded #ifdef CFG_RISCV_SBI_CONSOLE

sbi_console.c has been assigned conditionally based on
CFG_RISCV_SBI_CONSOLE in sub.mk. Remove the #ifdef preprocessor
directive.

Si

riscv: sbi_console: remove unneeded #ifdef CFG_RISCV_SBI_CONSOLE

sbi_console.c has been assigned conditionally based on
CFG_RISCV_SBI_CONSOLE in sub.mk. Remove the #ifdef preprocessor
directive.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR

Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better
readability. Also, provide a function description.

Signed-off-by:

riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR

Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better
readability. Also, provide a function description.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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