core/arm32: support PL310 lockdown at TEE boot

Add routine arm_cl2_lockgit allways() that enable lock on all d/i ways.

Add config switch CFG_PL310_LOCKED. If set, at TEE boot, PL310 L2 cache
is ful

core/arm32: support PL310 lockdown at TEE boot

Add routine arm_cl2_lockgit allways() that enable lock on all d/i ways.

Add config switch CFG_PL310_LOCKED. If set, at TEE boot, PL310 L2 cache
is fully locked and invalidated. Once TZ as booted, NSec inherits from
a pre-configured L2 cache, pre-enable, but bypassed as all ways are
locked. If NSec wants to benefit from L2 cache, it shall unlock all
d/i ways.
Default setup: CFG_PL310_LOCKED is not defined. Linux may not integrate
the outercache unlock sequence at l2x0 inits.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

Reviewed-on: https://gerrit.st.com/17088
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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[plat-stm] cache_maintenance_l2() performed on given area

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Br

[plat-stm] cache_maintenance_l2() performed on given area

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Refactored version of cache_maintenance_l2() functions

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand

Refactored version of cache_maintenance_l2() functions

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Disable TEX Remap before enable MMU

- Add write_ats1cpw() and read_par() for page description debug
- Clear TEX bit beofre enable MMU

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens W

Disable TEX Remap before enable MMU

- Add write_ats1cpw() and read_par() for page description debug
- Clear TEX bit beofre enable MMU

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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sunxi: fix parallel build errors

Fixes https://github.com/OP-TEE/optee_os/issues/181.

plat-sunxi/link.mk uses CPP to generate its core linker script.
Commit a3911433960a ("core: get value of CFG_ v

sunxi: fix parallel build errors

Fixes https://github.com/OP-TEE/optee_os/issues/181.

plat-sunxi/link.mk uses CPP to generate its core linker script.
Commit a3911433960a ("core: get value of CFG_ variables directly from
generated/conf.h") has modified the core CPP flags to include conf.h
automatically, so one must make sure that this file exists when the linker
script is generated. This is done by adding a dependency on $(conf-file).

The vexpress platforms also lack the dependency, but the bug won't show
because of other dependencies which cause conf.h to be generated anyways.

PLATFORM=stm is fine because it does not use CPP.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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SE API: Change configuration to be prefixed with CFG_*

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

SE API: hide private interfaces

- Split each headers into module.h and module_priv.h, move the methods that
is only used internally by SE implementation to module_priv.h, and export
module_priv.

SE API: hide private interfaces

- Split each headers into module.h and module_priv.h, move the methods that
is only used internally by SE implementation to module_priv.h, and export
module_priv.h to rest of TEE Core
- Added new include path to se_api_self_tests.c for which needs to include
private headers
- Split aid.c and apdu.c from iso7816.c. Originally they have to be wriiten in
the same file since they share some private data structures. Now, the
private data structure can be shared via private headers.
- Split reader.c from manager.c for the same reason above.

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

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SE API: implment lubutee and svc handler

- Implemented tee_se_service
- Rename tee_se_reader_handle to tee_se_reader_proxy
to avoid confuse with libutee
- Implemented SE API(tee_internal_se_api.h)

SE API: implment lubutee and svc handler

- Implemented tee_se_service
- Rename tee_se_reader_handle to tee_se_reader_proxy
to avoid confuse with libutee
- Implemented SE API(tee_internal_se_api.h) in libutee
- Implemented svc handler for SE API
- rename protocol.[ch] to iso7816.[ch]
- prefix aid_* with "tee_se_"
- add an option to enable/disable se_api_self_tests

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

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SE API: Session, Protocol and Channel implementation

- Implement Session which maintains the connection between TA and a
specific SE Reader
- Implement ISO7816 transport layer protocol, and Channe

SE API: Session, Protocol and Channel implementation

- Implement Session which maintains the connection between TA and a
specific SE Reader
- Implement ISO7816 transport layer protocol, and Channel management
- Implement Utilities to handle AID(ISO7816-3) and APDU(ISO7816-4)
- Brunch of self tests to velidate functionality of each module

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

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SE API: SE Manager and Reader implementation

- Introduce an interface for developers to write reader driver
(core/include/tee/se/reader/interface.h)
- A sample reader driver implementation: PC/SC

SE API: SE Manager and Reader implementation

- Introduce an interface for developers to write reader driver
(core/include/tee/se/reader/interface.h)
- A sample reader driver implementation: PC/SC passthru reader
(core/tee/se/reader/passthru_reader)
- Currently supported machine is qemu-virt (compile with --with-pcsc-passthru)
- A selftest STA is included to test the functionality of SE Reader
(core/arch/arm32/sta/se_api_self_tests.c)
- To enable SE API, add "WITH_SE_API := y" in your platform config

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

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Introduce a Linux style initcall mechanism

To use it, simply add something like:

service_init(server_init_callback);

The callback regsitered will be invoked at the end of init_teecore().
Now we ha

Introduce a Linux style initcall mechanism

To use it, simply add something like:

service_init(server_init_callback);

The callback regsitered will be invoked at the end of init_teecore().
Now we have 2 priority service_init and driver_init. The callback
regsitered in service level will be invoked first.

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)

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SHA-1 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-1 implementation for LTC.
* Crypto extension based SHA-1 implementation is enabled for
plat-vexpress-juno.

Si

SHA-1 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-1 implementation for LTC.
* Crypto extension based SHA-1 implementation is enabled for
plat-vexpress-juno.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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SHA-256 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-256 implementation for LTC.
* Crypto extension based SHA-256 implementation is enabled for
plat-vexpress-ju

SHA-256 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-256 implementation for LTC.
* Crypto extension based SHA-256 implementation is enabled for
plat-vexpress-juno.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: support for VFP/NEON operations.

CFG_WITH_VFP=y enables use of VFP/NEON by context switching VFP state on
demand.

plat-vexpress: specific initialization of CPACR to allow CP10 and CP11
acces

arm32: support for VFP/NEON operations.

CFG_WITH_VFP=y enables use of VFP/NEON by context switching VFP state on
demand.

plat-vexpress: specific initialization of CPACR to allow CP10 and CP11
access to allow usage of VFP/NEON operations.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-vexpress: config nsacr

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

Add plat-sunxi

Initial version support for Allwinner A80 platform.
Allwinner A80 is big.little archtecture with 4*A7 + 4*A15,
Support Trustzone tech and secureboot inside hardware.
plat-sunxi suppor

Add plat-sunxi

Initial version support for Allwinner A80 platform.
Allwinner A80 is big.little archtecture with 4*A7 + 4*A15,
Support Trustzone tech and secureboot inside hardware.
plat-sunxi support features:
1.Clone plat-sunxi from plat-vexpress;
2.Secure bootloader reserved 64MB secure DRAM for optee_os;
3.Support SMP secondary cpu secure stage bootup;
4.Add uart driver to core/driver/*;
5.Support GIC driver initialization.
The porting work test on Optimus board, with allwinner A80 chip.

Signed-off-by: sunny <sunny@allwinnertech.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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ta_dev_kit.mk: get platform-specific flags from platform_flags.mk

Platform-specific flags that apply to user-mode code are moved from
from core/arch/$(ARCH)/plat-$(PLATFORM)/conf.mk to a new file:
c

ta_dev_kit.mk: get platform-specific flags from platform_flags.mk

Platform-specific flags that apply to user-mode code are moved from
from core/arch/$(ARCH)/plat-$(PLATFORM)/conf.mk to a new file:
core/arch/$(ARCH)/plat-$(PLATFORM)/platform_flags.mk.

This file is used by ta/mk/ta_dev_kit.mk so that the Trusted Applications
are built with the same flags used when building the user-mode TEE code.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: get value of CFG_ variables directly from generated/conf.h

Add a '-include' preprocessor flag to the command line so that all
TEE core files include generated/conf.h automatically. Then, there

core: get value of CFG_ variables directly from generated/conf.h

Add a '-include' preprocessor flag to the command line so that all
TEE core files include generated/conf.h automatically. Then, there
is no need to define macros via the command line (-DCFG_XYZ=...).

This commit also fixes a compile error when
CFG_TEE_CORE_EMBED_INTERNAL_TESTS=0.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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Align plat-stm and plat-vexpress versions of core_bootcfg.c

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.

Align plat-stm and plat-vexpress versions of core_bootcfg.c

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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plat-stm: move memory definition in platform_config.h

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-stm: rename memory definition name

Rename following memory area definition name, according
to the one used in vexpress:
CFG_DDR_START into DRAM0_BASE
CFG_DDR_SIZE

plat-stm: rename memory definition name

Rename following memory area definition name, according
to the one used in vexpress:
CFG_DDR_START into DRAM0_BASE
CFG_DDR_SIZE into DRAM0_SIZE
CFG_DDR1_START into DRAM1_BASE
CFG_DDR1_SIZE into DRAM1_SIZE
CFG_DDR_ARM_ARMTZ_START into CFG_SHMEM_START
CFG_DDR_ARM_ARMTZ_SIZE into CFG_SHMEM_SIZE
CFG_DDR_ARMTZ_ONLY_START into TZDRAM_BASE
CFG_DDR_ARMTZ_ONLY_SIZE into TZDRAM_SIZE

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: make stacks cache line aligned

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.or

plat-stm: make stacks cache line aligned

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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arm32: remove memmap_notinit bookkeeping

Removes the bookkeeping of whether memory map has been initialized or
not using the memmap_notinit variable. Memory map is always initialized
before any core

arm32: remove memmap_notinit bookkeeping

Removes the bookkeeping of whether memory map has been initialized or
not using the memmap_notinit variable. Memory map is always initialized
before any core_va2pa() or core_pa2va() is performed so the bookkeeping
doesn't do much good.

The variable was updated with caches disabled while other CPUs might have
caches enabled. This can result in unexpected problems.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-vexpress: make stacks cache line aligned

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

arm32: paging of TEE Core optionally enabled

plat-vexpress-*:
* Optionally enable paging with CFG_WITH_PAGER=y
* Uses fake SRAM when paging is enabled
* Supports partitioning OP-TEE binary in unpage

arm32: paging of TEE Core optionally enabled

plat-vexpress-*:
* Optionally enable paging with CFG_WITH_PAGER=y
* Uses fake SRAM when paging is enabled
* Supports partitioning OP-TEE binary in unpaged, init and pagable areas

plat-stm:
* Displays an error message if compiled with CFG_WITH_PAGER=y

arm32:
* Replaces legacy paging support with new paging support
* Removes unused tee_pager_unpg.c

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform - Check the code without the pager is not broken).

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