Change the access right from w to r in virt_to_phy

Currently we are using the write_ats1cpw to do the
virt_to_phys translation, but when the input address
is readonly, the translation will fail, fix

Change the access right from w to r in virt_to_phy

Currently we are using the write_ats1cpw to do the
virt_to_phys translation, but when the input address
is readonly, the translation will fail, fix it using
write_ats1cpr.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@huawei.com>

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plat-vexpress: configure tzc400 driver if enabled

Configures the tzc400 driver if CFG_TZC400 is y.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@

plat-vexpress: configure tzc400 driver if enabled

Configures the tzc400 driver if CFG_TZC400 is y.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: enable hardware RNG

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.o

plat-d02: enable hardware RNG

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>

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core: review assert and panic traces

Replace few "{ EMSG(...); panic(); }" with "panic(...);".

Disable file/line/func debug traces in panic() logs when
CFG_TEE_CORE_DEBUG is disable.

Change __asse

core: review assert and panic traces

Replace few "{ EMSG(...); panic(); }" with "panic(...);".

Disable file/line/func debug traces in panic() logs when
CFG_TEE_CORE_DEBUG is disable.

Change __assert_log() uses EMSG_RAW() to no pollute trace with
__assert_log() internals (duplicated file/line/func traces).

Change assert() to use a low/high verbosity mode upon
CFG_TEE_CORE_DEBUG as panic() does.

Change assert() to also trace the C function where assertion failed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jen.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

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core: remove TEE_ASSERT()

TEE_ASSERT() can be confusing regarding assert() as assert() can
be disabled through NDEBUG while TEE_ASSERT() can't.
Instead one should explicitly implement "if (cond) { p

core: remove TEE_ASSERT()

TEE_ASSERT() can be confusing regarding assert() as assert() can
be disabled through NDEBUG while TEE_ASSERT() can't.
Instead one should explicitly implement "if (cond) { panic(); }"

This patch removes several inclusions on tee_common_unpg.h as it
used to define TEE_ASSERT() that has been removed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jen.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

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assert/panic: fix misuse of assert/panic

Currently implementation of macro assert() does not expand to a
no-op when NDEBUG is defined. This will be done in a later change.
Before that, fix misuses o

assert/panic: fix misuse of assert/panic

Currently implementation of macro assert() does not expand to a
no-op when NDEBUG is defined. This will be done in a later change.
Before that, fix misuses of assert() and TEE_ASSERT():
- Correct misplaced assert() that should panic() whatever NDEBUG.
- Correct misplaced TEE_ASSERT() that should simply assert().

Also cleanup many inclusions of "assert.h" and few calls of assert().

Signed-off-by: Jens Wiklander <jen.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

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Simplify platform testing macros

Update the main Makefile so that PLATFORM_$(PLATFORM) and
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) are set to 'y', and add these
variables to the export list for the gener

Simplify platform testing macros

Update the main Makefile so that PLATFORM_$(PLATFORM) and
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) are set to 'y', and add these
variables to the export list for the generation of conf.h.

As a result, the definition of numerical flavor identifiers in the
multiple platform_config.h files is not needed anymore, and we can also
get rid of the PLATFORM_FLAVOR_IS() test macro. Instead, replace all
occurrences of '#if PLATFORM_FLAVOR_IS(foo)' with
'#if defined(PLATFORM_FLAVOR_foo)'.

This makes it possible to test the platform and not only the flavor in
any source file, so drop the manual definition of PLATFORM_hikey.

Finally, remove the definitions of platform_$(PLATFORM) and
platform_flavor_$(PLATFORM_FLAVOR) from core/core.mk since they are not
used.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

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Fix reversed order of carriage return and line feed..

..in console_putc() function.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

Add support for Hisilicon D02 (PLATFORM=d02)

D02 is a server-class development board equipped with a Hisilicon
Phosphor V660 processor (also called PV660, P660 or hip05).
The chip has 16 Cortex-A57

Add support for Hisilicon D02 (PLATFORM=d02)

D02 is a server-class development board equipped with a Hisilicon
Phosphor V660 processor (also called PV660, P660 or hip05).
The chip has 16 Cortex-A57 cores @ 2.1 GHz.

Note: '-mcpu=cortex-a57' causes the following warning, which doesn't
seem to have any adverse effect on OP-TEE and is registered as a
compiler bug [1]:

CC out/arm-plat-d02/core/lib/libtomcrypt/src/encauth/ccm/ccm_add_nonce.o
{standard input}: Assembler messages:
{standard input}:634: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67591

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

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Allow `_end` to be more than 1MB away from code

The PC relative load (`adr`) requires the destination label to be
within 1MB of the instruction itself. If for example, the HEAP_SIZE
is increased to

Allow `_end` to be more than 1MB away from code

The PC relative load (`adr`) requires the destination label to be
within 1MB of the instruction itself. If for example, the HEAP_SIZE
is increased too much, this can push the `_end` pass this limit.

Replace the single `adr` instruction with a pair (`adrp`, `add`) to
allow the symbol to load from any address.

Note that the increasing the heap size too much causes other failures.

Fixes #942.

Signed-off-by: David Brown <david.brown@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)

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drivers: add spi framework and pl022 driver

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklan

drivers: add spi framework and pl022 driver

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: rpc alloc check memory is valid

thread_rpc_alloc_arg() and thread_rpc_alloc_payload() only succeeds if
the allocated shared memory is valid shared memory.

Reviewed-by: etienne carriere <etien

core: rpc alloc check memory is valid

thread_rpc_alloc_arg() and thread_rpc_alloc_payload() only succeeds if
the allocated shared memory is valid shared memory.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Support CFG_TEE_CORE_NB_CORE > 8

Remove the stack_tmp_top[] array. Instead, compute the stack top for
each CPU in the assembly code:

sp = stack_tmp + (cpu_id + 1) * stack_tmp_stride

stack_tmp an

Support CFG_TEE_CORE_NB_CORE > 8

Remove the stack_tmp_top[] array. Instead, compute the stack top for
each CPU in the assembly code:

sp = stack_tmp + (cpu_id + 1) * stack_tmp_stride

stack_tmp and stack_tmp_stride are exported by thread.c.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: initialize tee_pager_tbl_info early

Initialize tee_pager_tbl_info early to support early address lookups in
MEM_AREA_TEE_RAM.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Teste

core: initialize tee_pager_tbl_info early

Initialize tee_pager_tbl_info early to support early address lookups in
MEM_AREA_TEE_RAM.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: use helper for tee_pager_tbl_info

Adds local helper variable for tee_pager_tbl_info to make the code
tidier.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Signed-off-by:

core: pager: use helper for tee_pager_tbl_info

Adds local helper variable for tee_pager_tbl_info to make the code
tidier.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_linear_map_end

Adds core_mmu_linear_map_end to short circuit some
phys_to_virt/virt_to_phys lookups.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Signed-off-by: Je

core: add core_mmu_linear_map_end

Adds core_mmu_linear_map_end to short circuit some
phys_to_virt/virt_to_phys lookups.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager replace TEE_PAGER_AREA_* with TEE_MATTR_*

Replaces TEE_PAGER_AREA_* attributes with corresponding
TEE_MATTR_* attributes.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Sig

core: pager replace TEE_PAGER_AREA_* with TEE_MATTR_*

Replaces TEE_PAGER_AREA_* attributes with corresponding
TEE_MATTR_* attributes.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tee_pager_handle_fault() returns true if OK

Change tee_pager_handle_fault() to return true if a fault has been
dealt with successfully or false if execution has to be aborted.

Reviewed-by: et

core: tee_pager_handle_fault() returns true if OK

Change tee_pager_handle_fault() to return true if a fault has been
dealt with successfully or false if execution has to be aborted.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu_populate_user_map() arguments

Replaces the struct tee_mmu_info *mmu argument for
core_mmu_populate_user_map() with struct user_ta_ctx *utc instead. This
affects a few other mmu functi

core: core_mmu_populate_user_map() arguments

Replaces the struct tee_mmu_info *mmu argument for
core_mmu_populate_user_map() with struct user_ta_ctx *utc instead. This
affects a few other mmu functions too.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_{set,get}_entry_primitive()

Adds core_mmu_set_entry_primitive() and core_mmu_get_entry_primitive()
and moves core_mmu_set_entry() and core_mmu_get_entry() to generic
translation t

core: add core_mmu_{set,get}_entry_primitive()

Adds core_mmu_set_entry_primitive() and core_mmu_get_entry_primitive()
and moves core_mmu_set_entry() and core_mmu_get_entry() to generic
translation table code.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32.h: add address translation functions

Adds more address translation functions that can be useful when
debugging.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wik

core: arm32.h: add address translation functions

Adds more address translation functions that can be useful when
debugging.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread: release locked unused stack pages

Before this patch when the pager is active the thread stacks uses demand
allocation to add required physical pages to the stacks, but those pages
are

core: thread: release locked unused stack pages

Before this patch when the pager is active the thread stacks uses demand
allocation to add required physical pages to the stacks, but those pages
are never returned to the pool of physical pages.

With this patch when pager is active the locked but currently unused
thread stack pages are released on thread free or RPC. This returns the
previously demand allocated physical pages to the pager.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Reviewed-by: David Brown <david.brown@linaro.org>
Tested-by: David Brown <david.brown@linaro.org> (qemu-32, FVP-64)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: add support to page out r/w pages

Adds support in pager to page out read-write pages by encrypting them
with AES-GCM to avoid leaking sensitive information. With this patch there
are th

core: pager: add support to page out r/w pages

Adds support in pager to page out read-write pages by encrypting them
with AES-GCM to avoid leaking sensitive information. With this patch there
are three different ways of providing virtual memory:
- read only, where each page is protected with a SHA-256 hash
- read write locked, corresponding with previous zero initialized where
mapped pages are removed from the usual pool of physical pages and
only returned on explicit release
- read write, *new* dirty read write pages triggers update to the
storage using encryption (AES-GCM) before the page is reused.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: add debug prints

Add debug prints that are triggered every 1024th page fault or when the
number of pages available to the pager changes. Useful to find out why
certain tests seems to run slow

pager: add debug prints

Add debug prints that are triggered every 1024th page fault or when the
number of pages available to the pager changes. Useful to find out why
certain tests seems to run slowly when the pager is enabled.

Enabled by CFG_TEE_CORE_DEBUG=y.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: add pager_aes_gcm_{de,en}crypt()

Adds pager_aes_gcm_decrypt() and pager_aes_gcm_encrypt() providing a
pager optimized AES-GCM implementation to be used with read/write
paging.

Reviewed-by: J

pager: add pager_aes_gcm_{de,en}crypt()

Adds pager_aes_gcm_decrypt() and pager_aes_gcm_encrypt() providing a
pager optimized AES-GCM implementation to be used with read/write
paging.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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