core: reimplement mobj_mapped_shm_alloc()

Now that normal registered shared memory (created with
mobj_reg_shm_alloc()) can be mapped the MOBJ type struct mobj_mapped_shm
is redundant.

With this pat

core: reimplement mobj_mapped_shm_alloc()

Now that normal registered shared memory (created with
mobj_reg_shm_alloc()) can be mapped the MOBJ type struct mobj_mapped_shm
is redundant.

With this patch mobj_mapped_shm_alloc() is reimplemented using
mobj_reg_shm_alloc() and mobj_reg_shm_map().

struct mobj_mapped_shm and all associated functions and variables are
removed.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add mobj_reg_shm_{,un}map()

Adds mobj_reg_shm_map() and mobj_reg_shm_unmap() operating on MOBJs
created with mobj_reg_shm_alloc(), also know as registered shared
memory.

mobj_reg_shm_alloc()

core: add mobj_reg_shm_{,un}map()

Adds mobj_reg_shm_map() and mobj_reg_shm_unmap() operating on MOBJs
created with mobj_reg_shm_alloc(), also know as registered shared
memory.

mobj_reg_shm_alloc() maps the described shared memory into OP-TEE OS
memory space, mobj_reg_shm_unmap() unmaps the same memory again.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mobj: remove double physical offset

Removes the double bookkeeping of physical offset into first physical
page of a MOBJ. Now all the different offsets are needed to calculate
the final offset

core: mobj: remove double physical offset

Removes the double bookkeeping of physical offset into first physical
page of a MOBJ. Now all the different offsets are needed to calculate
the final offset.

Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mobj: add mobj_get_phys_offs()

Adds mobj_get_phys_offs() which returns the physical offset into the
first physical page/section of a MOBJ.

Reviewed-by: Etienne Carriere <etienne.carriere@lina

core: mobj: add mobj_get_phys_offs()

Adds mobj_get_phys_offs() which returns the physical offset into the
first physical page/section of a MOBJ.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add Marvell platform with initial support for ARMADA A7K & A8K

Only tested 64-bit mode with default configurations:

1. build command
make PLATFORM=marvell-armada7080 CFG_ARM64_core=y
2. Passed

Add Marvell platform with initial support for ARMADA A7K & A8K

Only tested 64-bit mode with default configurations:

1. build command
make PLATFORM=marvell-armada7080 CFG_ARM64_core=y
2. Passed xtest

Signed-off-by: Kevin Peng <kevinp@marvell.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm: support registered shm buffers

CFG_DDR_SECURE_BASE/_SIZE can be used to define the DDR range reserved
to secure side. This can be larger than the TEETZ reserved memory.
If CFG_DDR_SECURE_B

plat-stm: support registered shm buffers

CFG_DDR_SECURE_BASE/_SIZE can be used to define the DDR range reserved
to secure side. This can be larger than the TEETZ reserved memory.
If CFG_DDR_SECURE_BASE/_SIZE is defined, plat-stm registers the
non-secure external memory to support dynamic shm registering.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core:sdp: fix SDP test pseudo-TA against dynamic shm

Physical memory typed CORE_MEM_NSEC_SHM belong to the default
contiguous shm memory. Since dynamic SHM, now non secure memory
reference can be ou

core:sdp: fix SDP test pseudo-TA against dynamic shm

Physical memory typed CORE_MEM_NSEC_SHM belong to the default
contiguous shm memory. Since dynamic SHM, now non secure memory
reference can be outside the default NSEC_SHM, hence check
non secure reference using CORE_MEM_NON_SEC type instead of
CORE_MEM_NSEC_SHM.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rcar: add non-secure DDR configuration

This patch adds non-secure DDR ranges for salvator-h3 and
salvator-m3 boards.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jens Wi

plat-rcar: add non-secure DDR configuration

This patch adds non-secure DDR ranges for salvator-h3 and
salvator-m3 boards.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rcar: add initial support for salvator-m3 board

Prior to this patch OP-TEE was able to run only at salvator-h3 board
(but it worked on salvator-m3 too, only by coincidence).

Signed-off-by: Vol

plat-rcar: add initial support for salvator-m3 board

Prior to this patch OP-TEE was able to run only at salvator-h3 board
(but it worked on salvator-m3 too, only by coincidence).

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rcar: force CFG_CORE_LARGE_PHYS_ADDR

On RCAR3 platform most of the DRAM is mapped over 4GB, so it needs
LPE enabled with 32-bit builds.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com

plat-rcar: force CFG_CORE_LARGE_PHYS_ADDR

On RCAR3 platform most of the DRAM is mapped over 4GB, so it needs
LPE enabled with 32-bit builds.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: allow TA unwind when cause of unwind is not abort

It is perfectly safe to run the call stack unwinding code on a paged TA
as long as we're not processing an abort. Adjust __abort_print()
acco

pager: allow TA unwind when cause of unwind is not abort

It is perfectly safe to run the call stack unwinding code on a paged TA
as long as we're not processing an abort. Adjust __abort_print()
accordingly.
Prior to this patch, the call stack was missing from TA panics if pager
was enabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-vexpress: juno: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0x180000000 for Juno.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wik

plat-vexpress: juno: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0x180000000 for Juno.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: fvp: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0xa00000000 for FVP.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wi

plat-vexpress: fvp: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0xa00000000 for FVP.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add register_phys_mem_ul()

Adds register_phys_mem_ul() which must be used (for compatibility with
CFG_CORE_LARGE_PHYS_ADDR=y) when input address and size is based on
symbols generated in the l

core: add register_phys_mem_ul()

Adds register_phys_mem_ul() which must be used (for compatibility with
CFG_CORE_LARGE_PHYS_ADDR=y) when input address and size is based on
symbols generated in the link script.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: trivial large paddr_t fixes

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Add CFG_CORE_LARGE_PHYS_ADDR for 64bit paddr_t

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: lpae: take nsec DDR ranges into account

Takes nsec DDR ranges into account when setting TCR.PS field.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander

core: lpae: take nsec DDR ranges into account

Takes nsec DDR ranges into account when setting TCR.PS field.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core.mk: make platform specific link.mk optional

Most platform do not need any special linker targets and so most
just link back to the default. Lets just have core.mk use the default
when a p

core: core.mk: make platform specific link.mk optional

Most platform do not need any special linker targets and so most
just link back to the default. Lets just have core.mk use the default
when a platform does not have this file. Also remove this from the
porting guidelines as it is now optional and only needed for advanced
use.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: link.mk: make platform specific kern.ld.S optional

Most platform do not need any special linker scripting and so most
just link back to the default. Lets just have link.mk use the default
when

core: link.mk: make platform specific kern.ld.S optional

Most platform do not need any special linker scripting and so most
just link back to the default. Lets just have link.mk use the default
when a platform does not have this file. Also remove this from the
porting guidelines as it is now optional and only needed for advanced
use.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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build: add CFG_DYN_SHM_CAP config variable

This variable can disable reported capability
OPTEE_SMC_SEC_CAP_DYNAMIC_SHM.

But dynamic SHM remains fully operational, though. This can be used
for testi

build: add CFG_DYN_SHM_CAP config variable

This variable can disable reported capability
OPTEE_SMC_SEC_CAP_DYNAMIC_SHM.

But dynamic SHM remains fully operational, though. This can be used
for testing and debugging to emulate system, where dynamic SHM is not
supported.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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entry_std.c: comment fixes in assign_mobj_to_param_mem()

- removed spaces before "?" in comments
- Capitalized first letter in first words

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com

entry_std.c: comment fixes in assign_mobj_to_param_mem()

- removed spaces before "?" in comments
- Capitalized first letter in first words

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: enable non-contiguous temporary reference parameters

Now, when we can pass list of pages between REE and TEE it is possible
to use temporary memory references that are not located in a preallo

core: enable non-contiguous temporary reference parameters

Now, when we can pass list of pages between REE and TEE it is possible
to use temporary memory references that are not located in a preallocated
shared memory area. By employing OPTEE_MSG_ATTR_NONCONTIG parameter
attribute, REE can provide own buffer as a temporary memory reference.

Actually, such parameters are indistinguishable from registered shared
memory references. So, when OP-TEE spots temporary memory reference with
OPTEE_MSG_ATTR_NONCONTIG attribute, it will create `mobj_reg_shm` for it.
After call was handled, it will free that mobj.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP, QEMU v7/v8)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno with and without pager)
Tested-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> (Rcar M3)

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core: add registered shared memory support

Normal world now can call OPTEE_MSG_CMD_REGISTER_SHM and
OPTEE_MSG_CMD_UNREGISTER_SHM functions to register/unregister
shared memory.

After that, it can u

core: add registered shared memory support

Normal world now can call OPTEE_MSG_CMD_REGISTER_SHM and
OPTEE_MSG_CMD_UNREGISTER_SHM functions to register/unregister
shared memory.

After that, it can use OPTEE_MSG_ATTR_TYPE_RMEM_* to reference
to that registered shared buffers.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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entry_std: save parameters attributes into local memory

Normal World can change contents of shared memory at any time.
Right now it does not pose any threat. But next patches
will rely on attribute

entry_std: save parameters attributes into local memory

Normal World can change contents of shared memory at any time.
Right now it does not pose any threat. But next patches
will rely on attribute values. Thus, we need to read
parameter attributes only once and then use this saved value.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Revert "core: core_mmu_v7: core_mmu_get_user_pgdir: remove duplicated code"

This reverts commit 3eb2ba74961b. core_mmu_set_info_table() sets
tbl_info->num_entries to NUM_L1_ENTRIES, not NUM_UL1_ENTR

Revert "core: core_mmu_v7: core_mmu_get_user_pgdir: remove duplicated code"

This reverts commit 3eb2ba74961b. core_mmu_set_info_table() sets
tbl_info->num_entries to NUM_L1_ENTRIES, not NUM_UL1_ENTRIES. So the
removed code was actually not duplicate.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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