core: fix missing unpaged constraint on mobj_with_fobj_get_pa()

mobj_with_fobj_get_pa() gets called when a TA crashed and core prints
some information about the TA. This change ensures the function

core: fix missing unpaged constraint on mobj_with_fobj_get_pa()

mobj_with_fobj_get_pa() gets called when a TA crashed and core prints
some information about the TA. This change ensures the function belongs
to an unpaged section.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ensure embedded DTB found trace is output once

Move info trace "Embedded DTB found" so that it is output only once
even when get_embedded_dt() is called several times.

Signed-off-by: Etienne

core: ensure embedded DTB found trace is output once

Move info trace "Embedded DTB found" so that it is output only once
even when get_embedded_dt() is called several times.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix core panic when CFG_UNWIND=n

This change fixes a core panic occurrence when a TA panics while core
is built with CFG_TEE_CORE_DEBUG=y and CFG_UNWIND=n.

When a TA panics while CFG_UNWIND=n

core: fix core panic when CFG_UNWIND=n

This change fixes a core panic occurrence when a TA panics while core
is built with CFG_TEE_CORE_DEBUG=y and CFG_UNWIND=n.

When a TA panics while CFG_UNWIND=n, the thread specific data holding
abort_type was not loaded prior this change. The abort sequence that
print information to the console dumps now does not attemp to dump
un-relevant CPU register content.

Prior this change, ARM32 code could panic since reading an invalid SPSR
value when printing CPU state to the console, with an error trace like:

E/TC:? 0 TA panicked with code 0xbeef
E/TC:? 0 assertion 'thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR' failed at core/arch/arm/include/kernel/misc.h:22 <get_core_pos>
E/TC:0 0 Panic at core/kernel/assert.c:28 <_assert_break>


Prior this change ARM64 code printed irrelevant CPU state information
as below:

E/TC:? 0 TA panicked with code 0xbeef
E/TC:? 0
E/TC:? 0 User TA undef-abort at address 0x0
E/TC:? 0 esr 0x00000000 ttbr0 0x200000e173020 ttbr1 0x00000000 cidr 0x0
E/TC:? 0 cpu #0 cpsr 0x00000000
E/TC:? 0 x0 0000000000000000 x1 0000000000000000
(...)
E/TC:? 0 x30 0000000000000000 elr 0000000000000000
E/TC:? 0 sp_el0 0000000000000000

Fixes: c0bc8d0e7d72 ("core: print TA stack dump from thread context")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move embedded DTB out of init sections

This change makes generic boot to discover non-secure memory and
console configuration from the external DTB only, no more from the
embedded DTB as prior

core: move embedded DTB out of init sections

This change makes generic boot to discover non-secure memory and
console configuration from the external DTB only, no more from the
embedded DTB as prior this change. When generic boot attempts to access
embedded DTB, the embedded DTB gets located in init read-only data
section become unnecessary too big. With this change, embedded DTB now
lies in the standard pageable read-only data section, relaxing memory
footprint constraint.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: update DTS files to Linux kernel 5.2-rc1

Synchronize stm32mp1 DTS files with those published in Linux kernel
source tree at commit a188339ca5a3 ("Linux 5.2-rc1").

This change updates plat

stm32mp1: update DTS files to Linux kernel 5.2-rc1

Synchronize stm32mp1 DTS files with those published in Linux kernel
source tree at commit a188339ca5a3 ("Linux 5.2-rc1").

This change updates platforms EV1 and ED1 and introduces DK1 and DK2
known as DiscoveryKit board. It also introduces stpmic1 bindings header
file needed for platform DTS files compilation.

Among other changes, this commit introduces STPMIC1 and BSEC description
nodes. STPMIC1 defines regulators. BSEC describes fuses and uses the
status / secure-status to define fuse access scope in the scope of BSEC
support.

This change strictly dumps Linux kernel DTS files into OP-TEE but
regarding stm32mp157c.dtsi for which the OP-TEE DTS file adds node
for the ETZPC device which is mandated by OP-TEE but not defined in
non-secure Linux kernel scope.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: provide struct user_ta_store_ops in public .h file

Moves struct user_ta_store_ops definition into the new
<kernel/user_ta_store.h> file.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro

core: provide struct user_ta_store_ops in public .h file

Moves struct user_ta_store_ops definition into the new
<kernel/user_ta_store.h> file.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Move reg_pair_*() to util.h

Moves the two functions reg_pair_to_64() and reg_pair_from_64() from the
core only .h file <kernel/misc.h> to the libutils .h file util.h to make
the functions available

Move reg_pair_*() to util.h

Moves the two functions reg_pair_to_64() and reg_pair_from_64() from the
core only .h file <kernel/misc.h> to the libutils .h file util.h to make
the functions available from TAs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: check utc->areas before assigning tables

In tee_pager_assign_uta_tables() check that utc->areas are allocated
before assigning tables. If utc->areas are not allocated, skip the
operatio

core: pager: check utc->areas before assigning tables

In tee_pager_assign_uta_tables() check that utc->areas are allocated
before assigning tables. If utc->areas are not allocated, skip the
operation.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: vm_set_prot(): skip prot bits already set

In vm_set_prot() skip a region which already has the requested
protection bits set as requested.

Acked-by: Etienne Carriere <etienne.carriere@linaro.

core: vm_set_prot(): skip prot bits already set

In vm_set_prot() skip a region which already has the requested
protection bits set as requested.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: Add in calls to set CAAM job-ring permissions

This patch adds a call to set CAAM job-ring permissions for i.MX6 and i.MX7
processors. Since the iMX6ULL does not have a CAAM it will be ski

core: imx: Add in calls to set CAAM job-ring permissions

This patch adds a call to set CAAM job-ring permissions for i.MX6 and i.MX7
processors. Since the iMX6ULL does not have a CAAM it will be skipped but,
all other i.MX6 and i.MX7 SoCs will have their default CAAM job-ring
permissions set to normal-world.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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core: imx: Add simple CAAM permissions set routine

When we transition to secure-world certain parts of the CAAM become opaque
to normal world. This patch adds a simple routine to set CAAM job-ring
p

core: imx: Add simple CAAM permissions set routine

When we transition to secure-world certain parts of the CAAM become opaque
to normal world. This patch adds a simple routine to set CAAM job-ring
permissions to normal-world by default.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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pta: fix spelling error in comment

Fix a spelling error in validate_in_param().

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-imx: conf: add ccimx6ulsbcpro

The Digi CCIMX6UL SBC Pro board support 256MB of RAM and the default
UART is UART5.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Pe

plat-imx: conf: add ccimx6ulsbcpro

The Digi CCIMX6UL SBC Pro board support 256MB of RAM and the default
UART is UART5.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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virt: kern.ld.S: remove PROVIDE() keyword

The linker script for the TEE core exports two symbols using the
PROVIDE() keyword. This keyword is not needed; it makes no difference
because when CFG_VIRT

virt: kern.ld.S: remove PROVIDE() keyword

The linker script for the TEE core exports two symbols using the
PROVIDE() keyword. This keyword is not needed; it makes no difference
because when CFG_VIRTUALIZATION=y the symbols are *not* defined
elsewhere, and they *are* used by a C file, so that a normal symbol will
do the same [1]. Therefore, remove the keyword.

[1]: https://sourceware.org/binutils/docs/ld/PROVIDE.html#PROVIDE
"The PROVIDE keyword may be used to define a symbol [...] only if it is
referenced but not defined."

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: fix stm32_get_gpio_bank_base()

Correct missing return in function stm32_get_gpio_bank_base(). Prior
this change, platform may fail to boot with debug trace:

E/TC:0 0 assertion 'bank <= GP

stm32mp1: fix stm32_get_gpio_bank_base()

Correct missing return in function stm32_get_gpio_bank_base(). Prior
this change, platform may fail to boot with debug trace:

E/TC:0 0 assertion 'bank <= GPIO_BANK_K' failed at core/arch/arm/plat-stm32mp1/main.c:311 <stm32_get_gpio_bank_base>

Fixes: 68c4a16b37c7 ("stm32mp1: use phys_to_virt_io_secure() where expected")

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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stm32mp1: power management for GPIOz

Ensure secure hardening of GPIOz bank pins is restored when resuming
from a low power state where configuration might be lost.

Signed-off-by: Etienne Carriere <

stm32mp1: power management for GPIOz

Ensure secure hardening of GPIOz bank pins is restored when resuming
from a low power state where configuration might be lost.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: counting GPIOZ bank pins

Get the GPIOZ bank pin count from the device tree. The shared
resources driver uses this information to validate GPIO pin numbers.

Signed-off-by: Etienne Carriere

stm32mp1: counting GPIOZ bank pins

Get the GPIOZ bank pin count from the device tree. The shared
resources driver uses this information to validate GPIO pin numbers.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: print TA stack dump from thread context

Instead of printing TA stack dump in abort mode, save the required
information and print it from user_ta_enter() in thread context. This
allows dumping

core: print TA stack dump from thread context

Instead of printing TA stack dump in abort mode, save the required
information and print it from user_ta_enter() in thread context. This
allows dumping the stack also for paged TAs.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: kern.ld.S: ignore .init section

The ELF .init section is meant to be used by program loaders to run
special initialization code before the main entry point is called. This
does not apply

core: arm: kern.ld.S: ignore .init section

The ELF .init section is meant to be used by program loaders to run
special initialization code before the main entry point is called. This
does not apply to the TEE core, and the compiler does not generate such
a section. Therefore, mentioning it in the linker script is useless.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC,

stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC, I2C are always secure (when embedded).

RNG uses a secure or non-secure mapping according to its registration in
platform shared_resource driver.

GPIOs IO memory is always access though non-secure mapped virtual
addresses.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce io_pa_or_va_{secure|nsec}()

io_pa_or_va_secure() returns the secure mapped virtual address
if MMU is enable while io_pa_or_va_nsec() would return the non-secure
mapped virtual addres

core: introduce io_pa_or_va_{secure|nsec}()

io_pa_or_va_secure() returns the secure mapped virtual address
if MMU is enable while io_pa_or_va_nsec() would return the non-secure
mapped virtual address.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: kern.ld.S: discard .interp section

tee.elf currently has an INTERP segment that contains
"/usr/lib/ld.so.1". This is totally meaningless, so remove it by
discarding the .interp section in

core: arm: kern.ld.S: discard .interp section

tee.elf currently has an INTERP segment that contains
"/usr/lib/ld.so.1". This is totally meaningless, so remove it by
discarding the .interp section in the linker script.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: bugfix mutex_destroy()

Prior to this patch mutex_destroy() was incorrectly testing the lock state.
With this patch the test is corrected to avoid panic() on unlocked mutexes.

Reviewed-by: Jer

core: bugfix mutex_destroy()

Prior to this patch mutex_destroy() was incorrectly testing the lock state.
With this patch the test is corrected to avoid panic() on unlocked mutexes.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ree_fs_ta.c: fix compile error

Fixes compile error with CFG_REE_FS_TA_BUFFERED=n:
core/arch/arm/kernel/ree_fs_ta.c:284:13: error: ‘ta_get_tag’ undeclared here (not in a function); did you mean

core: ree_fs_ta.c: fix compile error

Fixes compile error with CFG_REE_FS_TA_BUFFERED=n:
core/arch/arm/kernel/ree_fs_ta.c:284:13: error: ‘ta_get_tag’ undeclared here (not in a function); did you mean ‘ta_head’?
.get_tag = ta_get_tag,
^~~~~~~~~~
ta_head
core/arch/arm/kernel/ree_fs_ta.c:201:19: error: ‘ree_fs_ta_get_tag’ defined but not used [-Werror=unused-function]
static TEE_Result ree_fs_ta_get_tag(const struct user_ta_store_handle *h,
^~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
mk/compile.mk:147: recipe for target '../out-os-qemu/core/arch/arm/kernel/ree_fs_ta.o' failed

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: common SoC registers protections

Helper functions for stm32mp1 platform to access a SoC interface
register that can be accessed from several drivers and services.
They all use a common spi

stm32mp1: common SoC registers protections

Helper functions for stm32mp1 platform to access a SoC interface
register that can be accessed from several drivers and services.
They all use a common spinlock to ensure atomic update of the
register content.

Helpers: io_mask32_stm32shregs(), io_setbits32_stm32shregs(),
io_clrbits32_stm32shregs() and io_clrsetbits32_stm32shregs().

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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