History log of /optee_os/core/arch/ (Results 1851 – 1875 of 4033)
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59ac380121-Dec-2020 Jens Wiklander <jens.wiklander@linaro.org>

core: split boot_init_primary()

Splits boot_init_primary() into boot_init_primary_early() and
boot_init_primary_late(). The thread#0 stack pointer is assigned as
stack pointer before boot_init_prima

core: split boot_init_primary()

Splits boot_init_primary() into boot_init_primary_early() and
boot_init_primary_late(). The thread#0 stack pointer is assigned as
stack pointer before boot_init_primary_late() is called. This allows
functions registered to be called by call_finalcalls() to depend on the
full thread stack being available.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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955968a813-Jan-2021 Michael Scott <mike@foundries.io>

core: imx: remove security check for i.MX6DQ

Recent commit cfff3778dae0 ("core: imx: remove security check for
i.MX6SDL") fixed an issue where i.MX6SDL SoC does not expose the
security configuration

core: imx: remove security check for i.MX6DQ

Recent commit cfff3778dae0 ("core: imx: remove security check for
i.MX6SDL") fixed an issue where i.MX6SDL SoC does not expose the
security configuration in the HPSR registers correctly.

This issue also affects i.MX6DQ. Let's add a check for this SoC
family in the same place.

Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>

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7fb5f45404-Jan-2021 Jens Wiklander <jens.wiklander@linaro.org>

core: remove temporary external DT mapping

During boot the external DT is mapped while processing the DT. Once
OP-TEE is done with the DT it should be unmapped to avoid stale mappings
that might cau

core: remove temporary external DT mapping

During boot the external DT is mapped while processing the DT. Once
OP-TEE is done with the DT it should be unmapped to avoid stale mappings
that might cause problems later. Fix this by calling
core_mmu_rem_mapping() from release_external_dt() just before jumping to
normal world.

Fixes: https://github.com/OP-TEE/optee_os/issues/4278
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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a499fe1204-Jan-2021 Jens Wiklander <jens.wiklander@linaro.org>

core: ifdef frag_id member in struct dt_descriptor

The frag_id member in struct dt_descriptor is only used if
CFG_EXTERNAL_DTB_OVERLAY is defined, so make it conditional.

Acked-by: Etienne Carriere

core: ifdef frag_id member in struct dt_descriptor

The frag_id member in struct dt_descriptor is only used if
CFG_EXTERNAL_DTB_OVERLAY is defined, so make it conditional.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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507229d504-Jan-2021 Jens Wiklander <jens.wiklander@linaro.org>

core: add core_mmu_remove_mapping()

Adds core_mmu_remove_mapping() which removes mappings earlier added with
core_mmu_add_mapping().

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acke

core: add core_mmu_remove_mapping()

Adds core_mmu_remove_mapping() which removes mappings earlier added with
core_mmu_add_mapping().

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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cfff377824-Nov-2020 Rouven Czerwinski <r.czerwinski@pengutronix.de>

core: imx: remove security check for i.MX6SDL

The i.MX6SDL SoCs do not expose the security configuration in the HPSR
registers correctly, they always return SNVS_SECURITY_CFG_FAB (000),
however the

core: imx: remove security check for i.MX6SDL

The i.MX6SDL SoCs do not expose the security configuration in the HPSR
registers correctly, they always return SNVS_SECURITY_CFG_FAB (000),
however the SSM information is still exposed correctly.
Remove the check for the security configuration, since the bits all read
zero on these SoCs, even if they are securely booted.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Clement Faure <clement.faure@nxp.com>

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496551a906-Jan-2021 Jerome Forissier <jerome@forissier.org>

plat-imx, plat-rzn1: remove redundant recipes to generate tee-raw.bin

Since commit 5ae0290f7f3b ("core: kernel: link.mk: Move rules to generate
tee-raw.bin and tee.srec from rcar platform"), the rec

plat-imx, plat-rzn1: remove redundant recipes to generate tee-raw.bin

Since commit 5ae0290f7f3b ("core: kernel: link.mk: Move rules to generate
tee-raw.bin and tee.srec from rcar platform"), the recipe to produce
tee-raw.bin is in the common makefile core/arch/arm/kernel/link.mk.
Therefore the recipes in core/arch/arm/plat-imx/link.mk and
core/arch/arm/plat-rzn1/link.mk are redundant and need to be removed.
Fixes the following build warning:

$ make -s PLATFORM=imx-mx6ullevk
core/arch/arm/plat-imx/link.mk:7: warning: overriding recipe for target 'out/arm-plat-imx/core/tee-raw.bin'
core/arch/arm/kernel/link.mk:230: warning: ignoring old recipe for target 'out/arm-plat-imx/core/tee-raw.bin'

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>

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3312950516-Dec-2020 Jorge Ramirez-Ortiz <jorge@foundries.io>

plat-imx: do not enable CFG_CRYPTO_DRIVER with CFG_NXP_CAAM

Some IMX users might choose a different crypto driver (like the SE050)
but still require CAAM to provide the hardware unique key and perha

plat-imx: do not enable CFG_CRYPTO_DRIVER with CFG_NXP_CAAM

Some IMX users might choose a different crypto driver (like the SE050)
but still require CAAM to provide the hardware unique key and perhaps
the RNG - since reading the RNG over I2C can impact performance on
some platforms.

This commit allows for such configuration.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Clement Faure <clement.faure@nxp.com>

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baa5161d11-Dec-2020 Balint Dobszay <balint.dobszay@arm.com>

core: ldelf: implement separate syscalls for ldelf

Implements a separate syscall handler for ldelf to decouple it from user
TAs and enable using it for all TSs. The calling convention is the same
as

core: ldelf: implement separate syscalls for ldelf

Implements a separate syscall handler for ldelf to decouple it from user
TAs and enable using it for all TSs. The calling convention is the same
as for utee_* syscalls. To distinguish between the different SVCs, the
syscall handler pointer is updated before entering ldelf and restored
after returning. The step of opening a system PTA session and invoking
the commands there is eliminated, the necessary functionality is
implemented in the ldelf syscall functions.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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0a971fdb11-Dec-2020 Balint Dobszay <balint.dobszay@arm.com>

core: invoke SVC handler through struct ts_session

Store the current SVC handler function pointer in struct ts_session, and
invoke the handler through this. Enables changing the SVC handler for a
se

core: invoke SVC handler through struct ts_session

Store the current SVC handler function pointer in struct ts_session, and
invoke the handler through this. Enables changing the SVC handler for a
session without modifying the ts_ops defined in the session context.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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cbe7e1b811-Dec-2020 Balint Dobszay <balint.dobszay@arm.com>

core: extract ldelf related code from system PTA

Various functions in the system PTA are only used in conjunction with
ldelf. They either implement a system service needed only by ldelf
(system_open

core: extract ldelf related code from system PTA

Various functions in the system PTA are only used in conjunction with
ldelf. They either implement a system service needed only by ldelf
(system_open_ta_binary(), etc.) or they provide an interface for TAs to
invoke services implemented in user space by ldelf (call_ldelf_dlopen(),
call_ldelf_dlsym()). Extract these to a separate file as a first step
towards converting the PTA system_*() calls into proper ldelf-specific
syscalls.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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36bb435f11-Dec-2020 Balint Dobszay <balint.dobszay@arm.com>

core: move user_ctx field to struct ts_session

The user_ctx field in struct tee_ta_session is used by PTAs to keep
track of session specific information. Move it to struct ts_session to
make it gene

core: move user_ctx field to struct ts_session

The user_ctx field in struct tee_ta_session is used by PTAs to keep
track of session specific information. Move it to struct ts_session to
make it generic and reachable for all sessions, not just TAs. This
enables extracting ldelf related code from system PTA.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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9bbdacba04-Jan-2021 Jens Wiklander <jens.wiklander@linaro.org>

qemu_v8: configure secure interrupts

Configures GIC and enable reception of interrupts from the secure uart.
This enables testing of secure interrupts on the QEMU v8 platform by
typing in the secure

qemu_v8: configure secure interrupts

Configures GIC and enable reception of interrupts from the secure uart.
This enables testing of secure interrupts on the QEMU v8 platform by
typing in the secure log.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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145ae44602-Dec-2020 Jens Wiklander <jens.wiklander@linaro.org>

Use barrier_read_cntpct() to read CNTPCT

Arm ARM quite clearly mentions [1] [2] that such reads must be preceded
by an ISB to forbid re-ordering.

[1] https://developer.arm.com/documentation/ddi0487

Use barrier_read_cntpct() to read CNTPCT

Arm ARM quite clearly mentions [1] [2] that such reads must be preceded
by an ISB to forbid re-ordering.

[1] https://developer.arm.com/documentation/ddi0487/fc/ page D13-2863
"Synchronization requirements for AArch64 System registers" and page
G8-6146 "Ordering of reads of System registers".
[2] https://developer.arm.com/documentation/ddi0406/cd/ page B3-1441
"Ordering of reads of system control registers"

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reported-by: Olivier Deprez <Olivier.Deprez@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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e19a75cb15-Dec-2020 Jens Wiklander <jens.wiklander@linaro.org>

core: add barrier_read_cntpct()

Adds barrier_read_cntpct() to arm.h. To be used as a helper when reading
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <eti

core: add barrier_read_cntpct()

Adds barrier_read_cntpct() to arm.h. To be used as a helper when reading
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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8bdc52f714-Dec-2020 Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

plat-rockchip: mark parameters as __maybe_unused in platform_secure_ddr_region

The weak variant of platform_secure_ddr_region() only emits a message
that the target region won't get protected due to

plat-rockchip: mark parameters as __maybe_unused in platform_secure_ddr_region

The weak variant of platform_secure_ddr_region() only emits a message
that the target region won't get protected due to missing platform-code.

Depending on the log-level this can result in the function parameters not
getting used at all, so mark them as __maybe_unused.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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0d016aff12-Dec-2020 Etienne Carriere <etienne.carriere@linaro.org>

core: fix user mode context reference in pager

Fix tee_pager_gpt_save_and_release_entries() to use to_user_mode_ctx()
to get current context user memory areas instead of to_user_ta_ctx()
since the f

core: fix user mode context reference in pager

Fix tee_pager_gpt_save_and_release_entries() to use to_user_mode_ctx()
to get current context user memory areas instead of to_user_ta_ctx()
since the former supports both SP and TA contexts.

Prior this change was pager asserting with an error trace like below:
E/TC:0 0 assertion 'is_user_ta_ctx(ctx)' failed at core/arch/arm/include/kernel/user_ta.h:56 <to_user_ta_ctx>
E/TC:0 0 Panic at core/kernel/assert.c:28 <_assert_break>

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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4055cfc402-Dec-2020 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Initial support for Renesas RZ/G2{H,M,N,E} SoC's

This patch adds support for Renesas RZ/G2{H,M,N,E} SoC's.

* Compiled with:
| make PLATFORM=rzg # Defaults to RZ/G2M SoC

Based on the work done

Initial support for Renesas RZ/G2{H,M,N,E} SoC's

This patch adds support for Renesas RZ/G2{H,M,N,E} SoC's.

* Compiled with:
| make PLATFORM=rzg # Defaults to RZ/G2M SoC

Based on the work done from Huynh Thanh Hung for RZ/G2 internally and
similar work done for Renesas RCar-Gen3 SoC's in mainline OP-TEE OS.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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5ae0290f10-Dec-2020 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

core: kernel: link.mk: Move rules to generate tee-raw.bin and tee.srec from rcar platform

Move the rules to generate tee-raw.bin and tee.srec from rcar platform to
core/arch/arm/kernel/link.mk so th

core: kernel: link.mk: Move rules to generate tee-raw.bin and tee.srec from rcar platform

Move the rules to generate tee-raw.bin and tee.srec from rcar platform to
core/arch/arm/kernel/link.mk so that similar platforms can re-use it.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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5cc9ca5804-Dec-2020 Marouene Boubakri <marouene.boubakri@nxp.com>

core: kernel: link.mk: make path to kernel linker script generic

The path to kernel script is hard-coded. Despite it is in a arch specific
folder, it should use defined variables.
This is helpful in

core: kernel: link.mk: make path to kernel linker script generic

The path to kernel script is hard-coded. Despite it is in a arch specific
folder, it should use defined variables.
This is helpful in case of porting OP-TEE OS to a new architecture such we
make maximum reuse of existing sources.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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d53c018305-Jul-2019 Fabien Parent <fparent@baylibre.com>

plat-mediatek: add support for MT8183 SoC

Add OP-TEE support for MT8183 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

1dd81b5013-Feb-2020 Fabien Parent <fparent@baylibre.com>

plat-mediatek: Add support for GIC

Add the support for the GIC for the MediaTek platforms.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.or

plat-mediatek: Add support for GIC

Add the support for the GIC for the MediaTek platforms.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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f3368ec827-Nov-2020 Jerome Forissier <jerome@forissier.org>

core: arm: kern.ld.S: fix ROUNDUP() and ROUNDDOWN() for Clang

Fixes exceptions on boot when CFG_WITH_ASLR=y CFG_WITH_PAGER=y and the
Clang toolchain is used (tested with QEMUv8 and Clang 11.0.0).

T

core: arm: kern.ld.S: fix ROUNDUP() and ROUNDDOWN() for Clang

Fixes exceptions on boot when CFG_WITH_ASLR=y CFG_WITH_PAGER=y and the
Clang toolchain is used (tested with QEMUv8 and Clang 11.0.0).

The Clang linker happens to generate non-relocatable references to
symbols defined by expressions in the linker script which involve
some arithmetic operations on another symbol. More specifically, when
rounding up or down addresses to page boundaries using the expressions
defined in <util.h>. This commit introduces different ways of doing
ROUNDUP() and ROUNDDOWN() which work with both Clang and GCC:
- ROUNDUP() is replaced with the linker ALIGN() built-in function,
- ROUNDDOWN() is rewritten as 'symbol - something'.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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eb5f87aa26-Nov-2020 Jerome Forissier <jerome@forissier.org>

core: arm: kern.ld.S: remove redundant line

__rodata_init_end is defined twice. Remove one instance.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wikland

core: arm: kern.ld.S: remove redundant line

__rodata_init_end is defined twice. Remove one instance.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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c232eb8d12-Nov-2020 Etienne Carriere <etienne.carriere@linaro.org>

core: stmm: remove useless return values to local svc handlers

Remove the boolean return value from local functions
stmm_handle_mem_mgr_service(), stmm_handle_storage_service(),
spm_eret_error() and

core: stmm: remove useless return values to local svc handlers

Remove the boolean return value from local functions
stmm_handle_mem_mgr_service(), stmm_handle_storage_service(),
spm_eret_error() and spm_handle_direct_req() that all end
returning to secure partition (StMM) execution. Rename
return_helper() to return_from_sp_helper() and remove its
return value as it only prepare returning to SP caller.
No functional change.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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