plat: rcar: disable aarch32 support for OP-TEE core

While it is theoretically possible to boot RCar Gen3 SoC in aarch32
mode, it isn't supported by Renesas BSP. ARM TF provided by Renesas
boots only

plat: rcar: disable aarch32 support for OP-TEE core

While it is theoretically possible to boot RCar Gen3 SoC in aarch32
mode, it isn't supported by Renesas BSP. ARM TF provided by Renesas
boots only in aarch64 mode. Also it lacks aarch32 assembler code, so
it is not possible to built it for aarch32 at all.

Therefore, there is a little sense in supporting aarch32 in
OP-TEE (for plat-rcar, of course) - user just can't boot it. On other
hand it requires additional efforts to maintain aarch32 assembly code
that newer will be used.

This patch enforces CFG_ARM64_core build option and removes all
aarch32 related parts.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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boot: introduce plat_get_aslr_seed()

Platforms may provide own ways to get ASLR seed, so this commit
adds weak function plat_get_aslr_seed(), which is called when we
can't obtain seed from FDT.

Sig

boot: introduce plat_get_aslr_seed()

Platforms may provide own ways to get ASLR seed, so this commit
adds weak function plat_get_aslr_seed(), which is called when we
can't obtain seed from FDT.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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plat-vexpress: FF-A: update secondary core init

Currently when using FF-A on FVP platform, the secondary core entrypoint
registration is done with PSCI calls. However, this relies on a forked
TF-A v

plat-vexpress: FF-A: update secondary core init

Currently when using FF-A on FVP platform, the secondary core entrypoint
registration is done with PSCI calls. However, this relies on a forked
TF-A version, as normally PSCI calls aren't accepted from SWd. Replace
this mechanism with FFA_SECONDARY_EP_REGISTER, which is an FF-A v1.1
ALP0 ABI and it's supported by upstream TF-A v2.5.

Note that the Function ID expected by TF-A differs from the one in the
spec, this will be fixed when the spec is finalized, but the overall
mechanism should stay the same.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: a32: fix parameter passing for __thread_std_smc_entry()

With the commit referred below is __thread_std_smc_entry() changed to
take 6 arguments instead of 4. This means with the arm32 calling
c

core: a32: fix parameter passing for __thread_std_smc_entry()

With the commit referred below is __thread_std_smc_entry() changed to
take 6 arguments instead of 4. This means with the arm32 calling
convention [1] that the last two parameters are passed on the stack.
This is handled automatically by the C compiler, but has to be done by
hand when calling from assembly. __thread_std_smc_entry() is called from
assembly so fix the two places where the function is called.

Link [1]: https://developer.arm.com/documentation/ihi0042/latest/

Fixes: 4107d2f93e3e ("core: add a4 and a5 to thread_alloc_and_run()")
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix thread_alloc_and_run() argument passing

Fix thread_alloc_and_run() to pass all its arguments to
__thread_alloc_and_run(). This is needed with FF-A since the offset of
the struct optee_msg_

core: fix thread_alloc_and_run() argument passing

Fix thread_alloc_and_run() to pass all its arguments to
__thread_alloc_and_run(). This is needed with FF-A since the offset of
the struct optee_msg_arg is passed in w6 from normal world. The Linux
kernel driver currently passes offset=0 so it's not seen while testing,
but that may change with future optimizations in the kernel driver.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add support for i.MX 8MP EVK

Add support for mx8mp platforms

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens

core: imx: add support for i.MX 8MP EVK

Add support for mx8mp platforms

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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imx: pm: add support for reset2 function

Add support for SYSTEM_RESET2, which asserts WDOG-generated reset signal
WDOG_RESET_B_DEB (internal reset).

For additional details check WDOGx_WCR fields de

imx: pm: add support for reset2 function

Add support for SYSTEM_RESET2, which asserts WDOG-generated reset signal
WDOG_RESET_B_DEB (internal reset).

For additional details check WDOGx_WCR fields description in iMX
Applications Processor Reference Manual.

Acked-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: sm: upgrade to PSCI 1.1

Add support for new functions, introduced in PSCI v1.1 spec [1] (all
are optional):
* SYSTEM_RESET2 - extends existing SYSTEM_RESET. It provides

core: arm: sm: upgrade to PSCI 1.1

Add support for new functions, introduced in PSCI v1.1 spec [1] (all
are optional):
* SYSTEM_RESET2 - extends existing SYSTEM_RESET. It provides
architectural reset definitions and vendor-specific
resets.
* MEM_PROTECT - provides protection against cold reboot attacks,
by ensuring that memory is overwritten before it is
handed over to an operating system loader.
* MEM_PROTECT_CHECK_RANGE - used to check whether a memory range is
protected by MEM_PROTECT.

[1] https://developer.arm.com/documentation/den0022/latest/

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: sm: replace function ids with hex values

Replace PSCI function id defines with full hex values, so it's easier
to validate existing values/add new one from PSCI spec updates.

Reviewed-by

core: arm: sm: replace function ids with hex values

Replace PSCI function id defines with full hex values, so it's easier
to validate existing values/add new one from PSCI spec updates.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: fix thread_disable_prealloc_rpc_cache()

Fixes thread_disable_prealloc_rpc_cache() to also NULL rpc_mobj when
freeing the shared memory object. Failing to do so might cause it
rpc_mobj pointer

core: fix thread_disable_prealloc_rpc_cache()

Fixes thread_disable_prealloc_rpc_cache() to also NULL rpc_mobj when
freeing the shared memory object. Failing to do so might cause it
rpc_mobj pointer to be used after free.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arch/arm/include/*.h: use U() for unsigned constants

Updates with the U() macro as described in the recently updated
coding guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked

core/arch/arm/include/*.h: use U() for unsigned constants

Updates with the U() macro as described in the recently updated
coding guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arch/arm/include/*.h: se BIT() and SHIFT_U32() macros

Uses the more safe BIT() and SHIFT_U32() macros instead of direct
shifting of 1 or some other constant integer.

Acked-by: Ruchika Gupta <r

core/arch/arm/include/*.h: se BIT() and SHIFT_U32() macros

Uses the more safe BIT() and SHIFT_U32() macros instead of direct
shifting of 1 or some other constant integer.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu.[ch]: use U() for unsigned constants

Updates with the U() macro as described in the recently updated coding
guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: J

core: core_mmu.[ch]: use U() for unsigned constants

Updates with the U() macro as described in the recently updated coding
guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: enable CAAM DSA

Enable CAAM DSA algorithm for all LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: imx: enable CAAM DSA

Enable CAAM DSA algorithm for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: rename struct tee_pager_area to vm_paged_region

Renames struct tee_pager_area to struct vm_paged_region and moves it
next to the declaration of struct vm_region. Since areas are now called
pag

core: rename struct tee_pager_area to vm_paged_region

Renames struct tee_pager_area to struct vm_paged_region and moves it
next to the declaration of struct vm_region. Since areas are now called
paged regions or regions also rename functions, variables and struct
members accordingly.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-E

core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-EL2 SPMC" in the FFA specification.

Compile with CFG_CORE_SEL2_SPMC=y

Note that this is an experimental feature, ABIs etc may have
incompatible changes.

This depends on using the FF-A v4 patchset in the Linux kernel.

Reviewed-by: Jelle Sels <jelle.sels@arm.com>
Co-developed-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: FF-A ABI updates

Updates structs and definitions to follow FF-A version 1.0.

Use the special hard coded UUID (486178e0-e7f8-11e3-bc5e-0002a5d5c51b)
for the SP OP-TEE is when compiled fo

core: spmc: FF-A ABI updates

Updates structs and definitions to follow FF-A version 1.0.

Use the special hard coded UUID (486178e0-e7f8-11e3-bc5e-0002a5d5c51b)
for the SP OP-TEE is when compiled for FF-A.

Updates the FF-A OP-TEE message ABI to make room for struct
optee_msg_arg to be used for RPC for OPTEE_FFA_YIELDING_CALL_WITH_ARG.

struct thread_ctx::rpc_arg for the current thread will always hold a
pointer to the struct optee_msg_arg to be used for RPC.

With this allocation of shared memory can be pushed up one layer and be
done via the struct optee_msg_arg so the
OPTEE_FFA_YIELDING_CALL_RETURN_ALLOC_*_SHM and
OPTEE_FFA_YIELDING_CALL_RETURN_FREE_*_SHM can be removed making the FF-A
ABI a bit less complicated.

Changes OPTEE_FFA_UNREGISTER_SHM to be a blocking call instead of a
yielding call.

Removes the unused OPTEE_FFA_YIELDING_CALL_REGISTER_SHM.

Updates the return values from yielding calls to use the TEE_Result
values instead of FF-A one to use the error code from the correct layer.

Defines OPTEE_MSG_FMEM_INVALID_GLOBAL_ID to 0xffffffffffffffffff which
is used as an invalid global id instead of 0.

This is an ABI breakage which must be done in sync with the FF-A v4
patchset in the Linux kernel.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add a4 and a5 to thread_alloc_and_run()

Adds two parameters a4 and a5 to thread_alloc_and_run(),
thread_std_smc_entry() and __thread_std_smc_entry().

Zeroes are passed where the new parameter

core: add a4 and a5 to thread_alloc_and_run()

Adds two parameters a4 and a5 to thread_alloc_and_run(),
thread_std_smc_entry() and __thread_std_smc_entry().

Zeroes are passed where the new parameters are not needed.

This prepares for the next update of the FF-A ABI for OP-TEE where among
other things one more register is used by
OPTEE_FFA_YIELDING_CALL_WITH_ARG.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: add read_cntvct()

Adds read_cntvct() to read Counter-timer Virtual Count register.

Note that arm32 already have this function.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-of

arm64: add read_cntvct()

Adds read_cntvct() to read Counter-timer Virtual Count register.

Note that arm32 already have this function.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add thread_smccc()

Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first

core: add thread_smccc()

Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first 8 registers is then saved in
the argument struct.

With the new flag CFG_CORE_SEL2_SPMC configures OP-TEE to work with a
SPMC at S-EL2 instead of the dispatcher at EL3. The SMC instruction
should not be used when working with a SPMC, OP-TEE should instead use
the HVC instruction in such a configuration.

Without a SPMC at S-EL2 OP-TEE works with the dispatcher at EL3 with no
changes.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must us

Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must use CNTVCT
instead of CNTPCT while the old physical OP-TEE must continue to use
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: let struct tee_pager_area span multiple translation tables

Extends struct tee_pager_area to be able to span multiple translation
tables avoiding the need to split ranges into multiple a

core: pager: let struct tee_pager_area span multiple translation tables

Extends struct tee_pager_area to be able to span multiple translation
tables avoiding the need to split ranges into multiple areas in case a
range crosses a translation table boundary.

Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: enable CAAM DH

Enabled CAAM DH algorithm for all LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

core: imx: enable CAAM DH

Enable CAAM DH algorithm for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>