core: mm: Set GP bit to enable BTI for TEE core

For all the descriptor entries marked with TEE_MATTR_PX, enable
GP bit if BTI is enabled.

TEE_MATTR_GUARDED attribute is also added here. This will b

core: mm: Set GP bit to enable BTI for TEE core

For all the descriptor entries marked with TEE_MATTR_PX, enable
GP bit if BTI is enabled.

TEE_MATTR_GUARDED attribute is also added here. This will be used
when creating mapping for user space.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: Add support for reading register ID_AA64PFR1_EL1

Register ID_AA64PFR1_EL1 provides information about
implemented PE features in AArch64 state. Read it to determine
if BTI mechanism is support

arm64: Add support for reading register ID_AA64PFR1_EL1

Register ID_AA64PFR1_EL1 provides information about
implemented PE features in AArch64 state. Read it to determine
if BTI mechanism is supported or not.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add BTI launch pads in aarch64 assembly files

Compiler adds BTI launchpads only in C source files. For
assembly files, BTI launchpad is also required at locations
where "br" is used and at the start

Add BTI launch pads in aarch64 assembly files

Compiler adds BTI launchpads only in C source files. For
assembly files, BTI launchpad is also required at locations
where "br" is used and at the start of the functions. This
needs to be added manually.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutils: asm.S : Introduce parameter _bti in FUNC's

There are few places where the original macros FUNC and LOCAL_FUNC
are used to define vector tables or exception vector tables.
To take care of s

libutils: asm.S : Introduce parameter _bti in FUNC's

There are few places where the original macros FUNC and LOCAL_FUNC
are used to define vector tables or exception vector tables.
To take care of such assembly code where BTI is not needed,
introduce new parameter _bti. If the _bti passed to the
function is not default, don't add BTI launchpad to the function.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: bti: Support building TEE core C files with BTI

When running with BTI enabled we need to ask the compiler to enable
generation of BTI landing pads. With this option enabled, all C
source file

arm64: bti: Support building TEE core C files with BTI

When running with BTI enabled we need to ask the compiler to enable
generation of BTI landing pads. With this option enabled, all C
source files compiled for TEE Core including the kernel versions
of libraries such as libutils.a will be compiled with BTI. This
also includes ldelf loader C files.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Move section .note.gnu.property after .text in lds files

It is observed that clang compiler sometimes places the
.note.gnu.property at offset 0. For TA's, the loader expects
the user_ta_header at th

Move section .note.gnu.property after .text in lds files

It is observed that clang compiler sometimes places the
.note.gnu.property at offset 0. For TA's, the loader expects
the user_ta_header at that location while for ldelf,
_ldelf_start() is expected at this point. To avoid such
conflicts place this section after the text section.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: use adr_l for global r/w variable threads

Replace an adr instruction with adr_l in thread_foreign_intr_exit to
make sure that the r/w global variable threads is accessible even if the
optee bi

core: use adr_l for global r/w variable threads

Replace an adr instruction with adr_l in thread_foreign_intr_exit to
make sure that the r/w global variable threads is accessible even if the
optee binary is very large.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arch: kernel: move spmc functions from thread.h to thread_spmc.h

It is more relevant to declare thread_spmc_populate_mobj_from_rx() and
thread_spmc_relinquish() in thread_spmc.h instead of thr

core: arch: kernel: move spmc functions from thread.h to thread_spmc.h

It is more relevant to declare thread_spmc_populate_mobj_from_rx() and
thread_spmc_relinquish() in thread_spmc.h instead of thread.h
Source file mobj_ffa.c makes use of these two functions, hence include
kernel/thread_spmc.h header.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: stmm: Increase the shared number of pages

Currently we only allow single page sharing for the StanAloneMM non-secure
world buffer. There are cases on EFI variables though which this isn't
eno

core: stmm: Increase the shared number of pages

Currently we only allow single page sharing for the StanAloneMM non-secure
world buffer. There are cases on EFI variables though which this isn't
enough. For example an EFI signature list (.esl) containing more than
two keys would fail since the payload is larger than a single page. So
let's bump the number to something more reasonable.

Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

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lib: libutils: trace.c: make print_core_id() architecture-independent

The function print_core_id() in is calling architecture-specific routines
to retrieve the core id. It is more relevant to create

lib: libutils: trace.c: make print_core_id() architecture-independent

The function print_core_id() in is calling architecture-specific routines
to retrieve the core id. It is more relevant to create a new abstract
function trace_ext_get_core_id() in lib/libutee/trace_ext.c that needs to
be implemented in the architecture-specific code. This is similar to
print_thread_id() which calls trace_ext_get_thread_id() implemented in
core/arch/arm/kernel/trace_ext.c

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: lpae: fix build with large number of CPU cores

A compile time assertion is triggered by the following command:

$ make -j10 -s PLATFORM=vexpress-qemu_armv8a CFG_TEE_CORE_NB_CORE=128 \

core: arm: lpae: fix build with large number of CPU cores

A compile time assertion is triggered by the following command:

$ make -j10 -s PLATFORM=vexpress-qemu_armv8a CFG_TEE_CORE_NB_CORE=128 \
CFG_LPAE_ADDR_SPACE_BITS=40
In file included from core/arch/arm/mm/core_mmu_lpae.c:61:
core/arch/arm/mm/core_mmu_lpae.c: In function ‘core_init_mmu_prtn_ta_core’:
lib/libutils/isoc/include/assert.h:30:24: error: duplicate case value
30 | switch (0) { case 0: case ((x) ? 1: 0): default : break; } \
| ^~~~
core/arch/arm/mm/core_mmu_lpae.c:697:2: note: in expansion of macro ‘COMPILE_TIME_ASSERT’
697 | COMPILE_TIME_ASSERT(MAX_XLAT_TABLES <
| ^~~~~~~~~~~~~~~~~~~
lib/libutils/isoc/include/assert.h:30:16: note: previously used here
30 | switch (0) { case 0: case ((x) ? 1: 0): default : break; } \
| ^~~~
core/arch/arm/mm/core_mmu_lpae.c:697:2: note: in expansion of macro ‘COMPILE_TIME_ASSERT’
697 | COMPILE_TIME_ASSERT(MAX_XLAT_TABLES <
| ^~~~~~~~~~~~~~~~~~~
core/arch/arm/mm/core_mmu_lpae.c:708:8: warning: unused variable ‘ret’ [-Wunused-variable]
708 | bool ret = false;
| ^~~

The type used for struct mmu_partition::user_l1_table_idx, currently
uint8_t, is not wide enough. Fix the issue by using uint8_t or uint16_t
based on the value of MAX_XLAT_TABLES.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: fix CAAM base address for i.MX8Q platforms

Fix CAAM base address for i.MX8QM/QXP platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@

core: imx: fix CAAM base address for i.MX8Q platforms

Fix CAAM base address for i.MX8QM/QXP platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: imx: add SC driver for i.MX8QM/QXP

Add the secure controller driver that implements:
- SCFW API
- SCU IPC functions
- SCU secure IPC initialization
The SCU driver relies on the MU driver

drivers: imx: add SC driver for i.MX8QM/QXP

Add the secure controller driver that implements:
- SCFW API
- SCU IPC functions
- SCU secure IPC initialization
The SCU driver relies on the MU driver to communicate with the security
controller.

Signed-off-by: Remi Koman <remi.koman@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: mmu: fix compile time assertion to allow 48-bit VA space

The compile time assertion on CFG_LPAE_ADDR_SPACE_BITS is inconsistent
with the one in <mm/core_mmu.h>. It should allow a 48-bit s

core: arm: mmu: fix compile time assertion to allow 48-bit VA space

The compile time assertion on CFG_LPAE_ADDR_SPACE_BITS is inconsistent
with the one in <mm/core_mmu.h>. It should allow a 48-bit size.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: lpae: remove always true conditional

The runtime conditional: 'if (CORE_MMU_BASE_TABLE_LEVEL == 0)' in
core_init_mmu_prtn_ta_core() is redundant with the preprocessor
conditional: '#if (CORE_M

core: lpae: remove always true conditional

The runtime conditional: 'if (CORE_MMU_BASE_TABLE_LEVEL == 0)' in
core_init_mmu_prtn_ta_core() is redundant with the preprocessor
conditional: '#if (CORE_MMU_BASE_TABLE_LEVEL == 0)'. Remove it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: lpae: delete unused variable

Variable 'ret' in is not used so remove it. Fixes the following warning:

$ make -j10 -s PLATFORM=vexpress-qemu_armv8a CFG_LPAE_ADDR_SPACE_BITS=40
core/arch/arm/

core: lpae: delete unused variable

Variable 'ret' in is not used so remove it. Fixes the following warning:

$ make -j10 -s PLATFORM=vexpress-qemu_armv8a CFG_LPAE_ADDR_SPACE_BITS=40
core/arch/arm/mm/core_mmu_lpae.c: In function ‘core_init_mmu_prtn_ta_core’:
core/arch/arm/mm/core_mmu_lpae.c:708:22: warning: unused variable ‘ret’ [-Wunused-variable]
708 | bool ret = false;
| ^~~

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: enable Atmel TRNG driver

Default embed Atmel TRNG in sama5d2 platform.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed

plat-sam: enable Atmel TRNG driver

Default embed Atmel TRNG in sama5d2 platform.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: include sama5d2.h file necessary for some values

Defines that are in platform_config.h uses values from sama5d2.h file.
Include it to avoid dependency problems.

Acked-by: Etienne Carriere

plat-sam: include sama5d2.h file necessary for some values

Defines that are in platform_config.h uses values from sama5d2.h file.
Include it to avoid dependency problems.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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core: kernel: introduce function is_embedded_dt()

This function will return true if passed DTB is same as Embedded DTB,
otherwise false

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-

core: kernel: introduce function is_embedded_dt()

This function will return true if passed DTB is same as Embedded DTB,
otherwise false

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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dts: stm32mp1: disable CRYP1 device

Don't enable CRYP1 support in OP-TEE core from ST boards supporting
stm32mp1 platform to comply with the upstream boards DTS files since
v5.11 [1] in Linux kernel

dts: stm32mp1: disable CRYP1 device

Don't enable CRYP1 support in OP-TEE core from ST boards supporting
stm32mp1 platform to comply with the upstream boards DTS files since
v5.11 [1] in Linux kernel that enables CRYP1 in non-secure world.

Link: [1] https://github.com/torvalds/linux/commit/b6aa35c7393680ee0a1286ca3b3237fd106ef896
Fixes: 5e64ae6796b7 ("crypto: stm32: use CRYP IP for CIPHER algorithms")
Reviewed-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: Fix warning in mobj_reg_shm_inc_map()

Fixes a -Wdeclaration-after-statement warning in mobj_reg_shm_inc_map()
core/arch/arm/mm/mobj_dyn_shm.c: In function ‘mobj_reg_shm_inc_map’:
core/arch/arm

core: Fix warning in mobj_reg_shm_inc_map()

Fixes a -Wdeclaration-after-statement warning in mobj_reg_shm_inc_map()
core/arch/arm/mm/mobj_dyn_shm.c: In function ‘mobj_reg_shm_inc_map’:
core/arch/arm/mm/mobj_dyn_shm.c:188:2: error: ISO C90 forbids mixed declarations and code [-Werror=declaration-after-statement]
uint32_t exceptions = cpu_spin_lock_xsave(&reg_shm_map_lock);
^~~~~~~~

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix warning in tee_time_get_ree_time()

Fixes a -Wdeclaration-after-statement warning in tee_time_get_ree_time():
core/arch/arm/kernel/tee_time.c: In function ‘tee_time_get_ree_time’:
core/arch

core: fix warning in tee_time_get_ree_time()

Fixes a -Wdeclaration-after-statement warning in tee_time_get_ree_time():
core/arch/arm/kernel/tee_time.c: In function ‘tee_time_get_ree_time’:
core/arch/arm/kernel/tee_time.c:58:2: error: ISO C90 forbids mixed declarations and code [-Werror=declaration-after-statement]
struct thread_param params = THREAD_PARAM_VALUE(OUT, 0, 0, 0);

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rzn1: Add Cortex-M3 start

The RZ/N1 platform contains a Cortex-M3 in addition to dual A7 cores.

Add CFG_BOOT_CM3 flat (default=y) to start the Cortex-M3 unit.

Signed-off-by: Ralph Siemsen <ra

plat-rzn1: Add Cortex-M3 start

The RZ/N1 platform contains a Cortex-M3 in addition to dual A7 cores.

Add CFG_BOOT_CM3 flat (default=y) to start the Cortex-M3 unit.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rzn1: fix unmasked register writes

When writing all 32 bits of a register, there is no need for iomask_32
which performs a read-modify-write operation. Not only is it faster, but
certain hardwa

plat-rzn1: fix unmasked register writes

When writing all 32 bits of a register, there is no need for iomask_32
which performs a read-modify-write operation. Not only is it faster, but
certain hardware registers are write-only or have side effects on read.

Using iomask_32 was found to cause the following issues on RZ/N1:
- accessing the I2C EEPROM gives timeout errors on read
- serial console drops characters on input (eg. when pasting)
Switching to io_write32 for non-masked writes fixes the issues.

Fixes: f1cf4b79 ("Add support for Renesas RZ/N1 platform")
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-mediatek: set SHMEM base address after TZDRAM

In order to avoid hole between TZDRAM and SHMEM memory, the Non-secure
static shared memory physical base address is set by default just
after the

plat-mediatek: set SHMEM base address after TZDRAM

In order to avoid hole between TZDRAM and SHMEM memory, the Non-secure
static shared memory physical base address is set by default just
after the secure RAM (TZDRAM):
SHMEM_START = TZDRAM_START + TZDRAM_SIZE

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Julien Masson <jmasson@baylibre.com>

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