plat-stm32mp1: remove SCMI0 channel index

Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2]

plat-stm32mp1: remove SCMI0 channel index

Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2].

Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-4-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-5-alexandre.torgue@foss.st.com
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: scmi_server: removed unused channel SCMI1

Remove this SCMI channel from DT bindings and platform driver as it is
unused.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.c

plat-stm32mp1: scmi_server: removed unused channel SCMI1

Remove this SCMI channel from DT bindings and platform driver as it is
unused.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 t

plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 that
will use each specific DT bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: conf: default disable ASLR

Default disable CFG_CORE_ASLR on stm32mp1. The platform memory
firewall does not allow secure world to access external DTB in
non-secure memory when MMU is

plat-stm32mp1: conf: default disable ASLR

Default disable CFG_CORE_ASLR on stm32mp1. The platform memory
firewall does not allow secure world to access external DTB in
non-secure memory when MMU is OFF, which is what the software attempts
to do when CFG_CORE_ASLR=y.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: conf: update RAM configuration

Align platform RAM configuration with TF-A.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.car

plat-stm32mp1: conf: update RAM configuration

Align platform RAM configuration with TF-A.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: conf: default heap size to 48kB when pager is on

Changes default heap size from 64kB to 48kB when pager is enabled.
The saved physical pages are assigned to pager pool.

Signed-off-by

plat-stm32mp1: conf: default heap size to 48kB when pager is on

Changes default heap size from 64kB to 48kB when pager is enabled.
The saved physical pages are assigned to pager pool.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: conf: allow BSEC writing in debug mode

Default embed support for burning fuses when in debug build configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Rev

plat-stm32mp1: conf: allow BSEC writing in debug mode

Default embed support for burning fuses when in debug build configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: conf: disable TA compression when pager is on

Disable CFG_EARLY_TA_COMPRESS when CFG_WITH_PAGER is enabled. With this
change, the TAs will not be compressed into the TEE binary. Now,

plat-stm32mp1: conf: disable TA compression when pager is on

Disable CFG_EARLY_TA_COMPRESS when CFG_WITH_PAGER is enabled. With this
change, the TAs will not be compressed into the TEE binary. Now, core
heap can be smaller than 64kB and platform can leverage that to assign
more physical pages in the pager pool.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-stm32mp1: conf: remove shared memory configuration

This change fully removes the reserved static shared memory
(CFG_SHMEM_START/CFG_SHMEM_SIZE) that is no more needed since U-Boot
and Linux bot

plat-stm32mp1: conf: remove shared memory configuration

This change fully removes the reserved static shared memory
(CFG_SHMEM_START/CFG_SHMEM_SIZE) that is no more needed since U-Boot
and Linux both use their standard system memory as TEE shared memory.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: riscv: plat-spike: console driver based on host-target interface

Spike doesn't yet model a UART but relies on RISC-V Host-Target Interface
(HTIF) to perform all I/O. It is a protocol allowing

core: riscv: plat-spike: console driver based on host-target interface

Spike doesn't yet model a UART but relies on RISC-V Host-Target Interface
(HTIF) to perform all I/O. It is a protocol allowing the target to access
host to perform console, storage etc. It requires special ELF symbols
tohost and fromhost. HTIF base address is set to 0x40008000.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
[jf: remove useless line continuation; initialize base to 0]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: riscv: add stmm and sp prototypes

Provide a declaration of functions is_sp_ctx(), is_stmm_ctx(), to_sp_ctx()
and to_stmm_ctx() to avoid build errors.

Signed-off-by: Marouene Boubakri <marouen

core: riscv: add stmm and sp prototypes

Provide a declaration of functions is_sp_ctx(), is_stmm_ctx(), to_sp_ctx()
and to_stmm_ctx() to avoid build errors.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: riscv: generic_ram_layout.h: ram layout configuration directives

The RAM layout is similar to the original one, use TD(D|S)RAM instead of
TZ(D|S)RAM referring to Trusted Domain (TD).
Keep the

core: riscv: generic_ram_layout.h: ram layout configuration directives

The RAM layout is similar to the original one, use TD(D|S)RAM instead of
TZ(D|S)RAM referring to Trusted Domain (TD).
Keep the directives for secure data path. SDP could be achieved later
using IOPMP.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ens

core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ensure memory
ordering using fence instruction.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: riscv: add tlb_helpers.h

The tlbi_asid() function is required by core/mm/vm.c
and tlbi_all() function is required by core/mm/core_mmu.c
Declare them in core/arch/riscv/include/kernel/tlb_helpe

core: riscv: add tlb_helpers.h

The tlbi_asid() function is required by core/mm/vm.c
and tlbi_all() function is required by core/mm/core_mmu.c
Declare them in core/arch/riscv/include/kernel/tlb_helpers.h

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: riscv: plat-spike: add platform configuration header file

Introduces a minimalist platform_config.h to be used by linker scripts.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>

core: riscv: plat-spike: add platform configuration header file

Introduces a minimalist platform_config.h to be used by linker scripts.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: riscv.mk: setup compiler for the RISC-V core module

Setup compiler for the risc-v core module on 32 and 64 bits definitions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com

core: riscv: riscv.mk: setup compiler for the RISC-V core module

Setup compiler for the risc-v core module on 32 and 64 bits definitions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

show more ...

riscv: create makefiles and directories tree for riscv

This commits creates the very first makefiles, directories and
subdirectories for RISC-V port. It also creates a new platform flavor
named plat

riscv: create makefiles and directories tree for riscv

This commits creates the very first makefiles, directories and
subdirectories for RISC-V port. It also creates a new platform flavor
named plat-spike. Spike is a reference functional RISC-V ISA simulator
which provides full system emulation and it is developed alongside the
RISC-V toolchain.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-k3: drivers: Fix SA2UL background firewall size

For GP devices this first firewall region should be a background region
that spans the whole address space managed by this firewall. This allows

plat-k3: drivers: Fix SA2UL background firewall size

For GP devices this first firewall region should be a background region
that spans the whole address space managed by this firewall. This allows
normal use of devices behind it even when not explicitly permitted.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-k3: drivers: Add SA2UL RNG driver

TI K3 family devices contain a set of crypto accelerators under
the umbrella device SA2UL. Add support for setting up the power
and firewalls for this device.

plat-k3: drivers: Add SA2UL RNG driver

TI K3 family devices contain a set of crypto accelerators under
the umbrella device SA2UL. Add support for setting up the power
and firewalls for this device. Then add support for the TRNG
sub-device.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-k3: Move TI-SCI setup out of HUK function

The TI-SCI components are used for more than just the hardware
unique key, move the setup out into a service_init so it is
not tied to just HUK.

While

plat-k3: Move TI-SCI setup out of HUK function

The TI-SCI components are used for more than just the hardware
unique key, move the setup out into a service_init so it is
not tied to just HUK.

While here remove the device check for HUK, it works on all
supported K3 devices.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-k3: drivers: ti-sci: Add support for setting firewall state

This adds support for the TI-SCI firewall messages:
* TI_SCI_MSG_FWL_SET
* TI_SCI_MSG_FWL_GET
* TI_SCI_MSG_FWL_CHANGE_OWNER

Signe

plat-k3: drivers: ti-sci: Add support for setting firewall state

This adds support for the TI-SCI firewall messages:
* TI_SCI_MSG_FWL_SET
* TI_SCI_MSG_FWL_GET
* TI_SCI_MSG_FWL_CHANGE_OWNER

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-k3: drivers: ti-sci: Add support for setting device state

This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Foriss

plat-k3: drivers: ti-sci: Add support for setting device state

This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by:

drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: armv7: fix ASLR error

With commit 528dabb28254 ("core: suppress text relocation on
stack_tmp_export") the stack pointer is calculated using a relative
address instead of based on an absolute a

core: armv7: fix ASLR error

With commit 528dabb28254 ("core: suppress text relocation on
stack_tmp_export") the stack pointer is calculated using a relative
address instead of based on an absolute address which is relocated with
ASLR enabled.

Prior to this on Armv7 we compensate for a relocation update for
stack_tmp_export_rel in reset_secondary() just after the stack pointer
was initialized. So now when the relocation update of stack_tmp_export_rel
is gone remove the compensating code too.

Fixes: 528dabb28254 ("core: suppress text relocation on stack_tmp_export")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: sp: handle memory regions w/o base address

The FF-A spec states that in the SP manifest a base address is not
mandatory for memory regions. If the field is not present, the specified
memory re

core: sp: handle memory regions w/o base address

The FF-A spec states that in the SP manifest a base address is not
mandatory for memory regions. If the field is not present, the specified
memory region must be allocated by the SPMC and mapped to the SP's
context.

A copy of the SP manifest fdt is used for passing the memory region
virtual addresses to the SP. Additional space is allocated when copying
the fdt so the originally not present base address fields can be added
later.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
[jf: edit description to avoid checkpatch spelling warning]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...