dts: stm32: add passive tamper sampling configuration for stm32mp15xx-dkx

Add a passive tamper sampling configuration for stm32mp15xx-dkx boards.

Signed-off-by: Gatien Chevallier <gatien.chevallier

dts: stm32: add passive tamper sampling configuration for stm32mp15xx-dkx

Add a passive tamper sampling configuration for stm32mp15xx-dkx boards.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add TAMP interrupt line for tamper events in stm32mp151.dtsi

Add the TAMP interrupt line in the stm32mp151.dtsi for tamper events
to handle the interrupt generation.

Signed-off-by: Gati

dts: stm32: add TAMP interrupt line for tamper events in stm32mp151.dtsi

Add the TAMP interrupt line in the stm32mp151.dtsi for tamper events
to handle the interrupt generation.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp2xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr

plat-stm32mp2: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp2xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp1xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr

plat-stm32mp1: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp1xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI RIF configuration for the stm32mp257f-ev1 board

Add the RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Et

dts: stm32: add EXTI RIF configuration for the stm32mp257f-ev1 board

Add the RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI node in stm32mp251

Add the EXTI support for stm32mp25 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

dts: stm32: update EXTI node in stm32mp151

Update the EXTI support for stm32mp15 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st

dts: stm32: update EXTI node in stm32mp151

Update the EXTI support for stm32mp15 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI node in stm32mp131

Add the EXTI support for stm32mp13 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

plat-stm32mp2: conf: support STM32MP21x SoC family

Add support for the STM32MP21x SoC family.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.che

plat-stm32mp2: conf: support STM32MP21x SoC family

Add support for the STM32MP21x SoC family.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add stm32mp215f-dk board

Add device tree files for stm32mp215f-dk.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st

dts: stm32: add stm32mp215f-dk board

Add device tree files for stm32mp215f-dk.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: st: introduce stm32mp21 SoCs family

STM32MP21 family is composed of 3 SoCs defined as following:

-STM32MP211: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, UART, SPI, I2

dts: st: introduce stm32mp21 SoCs family

STM32MP21 family is composed of 3 SoCs defined as following:

-STM32MP211: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ...

-STM32MP213: STM32MP211 + a second ETH, CAN-FD.

-STM32MP215: STM32MP213 + Display and CSI2.

A second diversity layer exists for security features/ A35 frequency:
-STM32MP21xY, "Y" gives information:
-Y = A means A35@1.2GHz + no CRYP IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no CRYP IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.

Available packages are:

STM32MP21xxAM: 14x14mm/TFBGA289 123 ios
STM32MP21xxAN: 11x11mm/VFBGA273 123 ios
STM32MP21xxAL: 10x10mm/VFBGA361 123 ios
STM32MP21xxAO: 8x8mm/VFBGA225 98 ios

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: amd: Add PS GPIO Support

Add PS GPIO Driver support for AMD Platforms.

The PS GPIO Controller is managed through the PS subsystem and
can operate in either the Secure World or the Non-Secu

drivers: amd: Add PS GPIO Support

Add PS GPIO Driver support for AMD Platforms.

The PS GPIO Controller is managed through the PS subsystem and
can operate in either the Secure World or the Non-Secure World.
The driver utilizes the Device Tree Blob (DTB) to determine whether the
PS GPIO Controller should be supported in the Secure World.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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core: fix asan for CFG_WITH_PAGER=n

Some fixes are needed to make CFG_CORE_SANITIZE_KADDRESS=y work both
with and without CFG_DYN_CONFIG=y.

Sanitizing stack addresses aren't supported with CFG_DYN_

core: fix asan for CFG_WITH_PAGER=n

Some fixes are needed to make CFG_CORE_SANITIZE_KADDRESS=y work both
with and without CFG_DYN_CONFIG=y.

Sanitizing stack addresses aren't supported with CFG_DYN_CONFIG=y
since it requires extensive changes in the ASAN framework.

The VCORE_FREE area is moved right before the .asan_shadow area.

init_asan() calls boot_mem_init_asan() to tag access to already
allocated boot memory.

entry_a32.S is updated to skip allowing access to stacks in the
.asan_shadow area for CFG_DYN_CONFIG=y since stacks are stored
elsewhere in that configuration.

entry_a64.S is updated to initialize the .asan_shadow area in the same
way as in entry_a32.S.

The .asan_shadow area is mapped explicitly in collect_mem_ranges()
instead of relying on the now non-existent coverage of
MEM_AREA_TEE_RAM_RW.

CFG_DYN_CONFIG=y and CFG_WITH_PAGER=y is not yet known to work.

Fixes: 1c1f8b65b5c6 ("core: mm: unify secure core and TA memory")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: mm: fix relocation of pointers in user_vpn2_table_va[]

The user_vpn2_table_va[] stores several pointers pointing to the level 2
page tables used by user TA. When CFG_CORE_ASLR=y, these pointe

riscv: mm: fix relocation of pointers in user_vpn2_table_va[]

The user_vpn2_table_va[] stores several pointers pointing to the level 2
page tables used by user TA. When CFG_CORE_ASLR=y, these pointers must
be relocated to ASLR VA as well. To fix this issue, we call
boot_mem_add_reloc() onto each element of user_vpn2_table_va[], so that
the pointers have a chance to be relocated by boot_mem_relocate() later.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: replace CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG

This commit replaces CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG since now
RISC-V also supports CFG_DYN_STACK_CONFIG.

Signed-off-by: Alvin Chang

core: replace CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG

This commit replaces CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG since now
RISC-V also supports CFG_DYN_STACK_CONFIG.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: dynamic allocation of thread_core_local and its stacks

Refer to commit 59724f223500 ("core: dynamic allocation of
thread_core_local and its stacks"), we implement the code for RISC-V
ar

core: riscv: dynamic allocation of thread_core_local and its stacks

Refer to commit 59724f223500 ("core: dynamic allocation of
thread_core_local and its stacks"), we implement the code for RISC-V
architecture. With CFG_DYN_STACK_CONFIG enabled, the thread_core_local
and the two stacks, tmp_stack and abt_stack, are dynamically allocated.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: describe scmi resources for stm32mp257f-ev1 board

Describe SCMI resources under "scmi" node in stm32mp25-st-scmi-cfg.dtsi
file. Resources are SCMI exposed clocks and resets.

This file w

dts: stm32: describe scmi resources for stm32mp257f-ev1 board

Describe SCMI resources under "scmi" node in stm32mp25-st-scmi-cfg.dtsi
file. Resources are SCMI exposed clocks and resets.

This file will be re-used for other STM32MP25 boards.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat: stm32mp2: make the platform ready to compile with SCP-Fw

STM32MP2 could use SCP-Fw to handle SCMI messages. By default this is
disabled, but it could be enable with these config:
CFG_SCMI_SC

plat: stm32mp2: make the platform ready to compile with SCP-Fw

STM32MP2 could use SCP-Fw to handle SCMI messages. By default this is
disabled, but it could be enable with these config:
CFG_SCMI_SCPFW=y
CFG_SCP_FIRMWARE=<path_to_SCP-Fw_srcs>

On STM32MP2, OP-TEE use the resources describe in the "scmi" device-tree
node to configure SCP-Fw.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: support Octo-SPI manager driver

Default enable Octo-SPI manager driver on stm32mp2x platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Eti

plat-stm32mp2: conf: support Octo-SPI manager driver

Default enable Octo-SPI manager driver on stm32mp2x platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: enable OSPI1 on stm32mp257f-ev1 board

Enable OSPI1 on stm32mp257f-ev1 board. Therefore, enable ommanager node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-

dts: stm32: enable OSPI1 on stm32mp257f-ev1 board

Enable OSPI1 on stm32mp257f-ev1 board. Therefore, enable ommanager node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add ommanager node to stm32mp251.dtsi

Add the Octo-SPI manager node to the stm32mp251.dtsi file. This peripheral
is a low-level interface that manages the pinmux and the multiplexing of

dts: stm32: add ommanager node to stm32mp251.dtsi

Add the Octo-SPI manager node to the stm32mp251.dtsi file. This peripheral
is a low-level interface that manages the pinmux and the multiplexing of
two instances of Octo-SPI interfaces.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: sysconfig: add OSPIs address mapping

This patch adds an API to handle OSPIs address mapping.
The different configurations are:
- OSPI1(256 MBytes), OSPI2(unmapped)
- OSPI1(192 MByte

plat-stm32mp2: sysconfig: add OSPIs address mapping

This patch adds an API to handle OSPIs address mapping.
The different configurations are:
- OSPI1(256 MBytes), OSPI2(unmapped)
- OSPI1(192 MBytes), OSPI2(64 MBytes)
- OSPI1(128 MBytes), OSPI2(128 MBytes)
- OSPI1(64 MBytes), OSPI2(192 MBytes)
- OSPI1(unmapped), OSPI2(256 MBytes).

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add the SYSCFG node in stm32mp251.dtsi

Add the SYSCFG node in the stm32mp251.dtsi file. This allows some devices
to access global system configuration registers.

Signed-off-by: Gatien C

dts: stm32: add the SYSCFG node in stm32mp251.dtsi

Add the SYSCFG node in the stm32mp251.dtsi file. This allows some devices
to access global system configuration registers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevalli

dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: mm: Fix VA base for canonical addresses

RISC-V defines the following virtual address rules:
- For Sv39 (39-bit VA), bits 63–39 all equal to bit 38 of VA
- For Sv48 (48-bit VA), bits 63–48 all

riscv: mm: Fix VA base for canonical addresses

RISC-V defines the following virtual address rules:
- For Sv39 (39-bit VA), bits 63–39 all equal to bit 38 of VA
- For Sv48 (48-bit VA), bits 63–48 all equal to bit 47 of VA
- For Sv57 (57-bit VA), bits 63–57 all equal to bit 56 of VA

In other words, the most-significant bits of VA base must be all one if
the highest SvXX address bit of VA is one.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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