riscv: include: add misc_arch.h

Nothing to define for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: riscv: include: introduce riscv.h header

Creates header file risc.v to define most of the RISC-V operations.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Car

core: riscv: include: introduce riscv.h header

Creates header file risc.v to define most of the RISC-V operations.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: define RISC-V instruction set architecture in encoding.h

Define standard RISC-V instruction opcodes, control and status registers.
This file is auto-generated from riscv-opcodes and it

core: riscv: define RISC-V instruction set architecture in encoding.h

Define standard RISC-V instruction opcodes, control and status registers.
This file is auto-generated from riscv-opcodes and it is subject of
regular updates.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: plat-spike: default configuration for Spike platform

This commit sets the build configuration for a minimalist core to run
on Spike platform.

Signed-off-by: Marouene Boubakri <marouene

core: riscv: plat-spike: default configuration for Spike platform

This commit sets the build configuration for a minimalist core to run
on Spike platform.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: plat-spike: console driver based on host-target interface

Spike doesn't yet model a UART but relies on RISC-V Host-Target Interface
(HTIF) to perform all I/O. It is a protocol allowing

core: riscv: plat-spike: console driver based on host-target interface

Spike doesn't yet model a UART but relies on RISC-V Host-Target Interface
(HTIF) to perform all I/O. It is a protocol allowing the target to access
host to perform console, storage etc. It requires special ELF symbols
tohost and fromhost. HTIF base address is set to 0x40008000.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
[jf: remove useless line continuation; initialize base to 0]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: add stmm and sp prototypes

Provide a declaration of functions is_sp_ctx(), is_stmm_ctx(), to_sp_ctx()
and to_stmm_ctx() to avoid build errors.

Signed-off-by: Marouene Boubakri <marouen

core: riscv: add stmm and sp prototypes

Provide a declaration of functions is_sp_ctx(), is_stmm_ctx(), to_sp_ctx()
and to_stmm_ctx() to avoid build errors.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: generic_ram_layout.h: ram layout configuration directives

The RAM layout is similar to the original one, use TD(D|S)RAM instead of
TZ(D|S)RAM referring to Trusted Domain (TD).
Keep the

core: riscv: generic_ram_layout.h: ram layout configuration directives

The RAM layout is similar to the original one, use TD(D|S)RAM instead of
TZ(D|S)RAM referring to Trusted Domain (TD).
Keep the directives for secure data path. SDP could be achieved later
using IOPMP.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ens

core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ensure memory
ordering using fence instruction.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: add tlb_helpers.h

The tlbi_asid() function is required by core/mm/vm.c
and tlbi_all() function is required by core/mm/core_mmu.c
Declare them in core/arch/riscv/include/kernel/tlb_helpe

core: riscv: add tlb_helpers.h

The tlbi_asid() function is required by core/mm/vm.c
and tlbi_all() function is required by core/mm/core_mmu.c
Declare them in core/arch/riscv/include/kernel/tlb_helpers.h

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: plat-spike: add platform configuration header file

Introduces a minimalist platform_config.h to be used by linker scripts.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>

core: riscv: plat-spike: add platform configuration header file

Introduces a minimalist platform_config.h to be used by linker scripts.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv.mk: setup compiler for the RISC-V core module

Setup compiler for the risc-v core module on 32 and 64 bits definitions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com

core: riscv: riscv.mk: setup compiler for the RISC-V core module

Setup compiler for the risc-v core module on 32 and 64 bits definitions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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riscv: create makefiles and directories tree for riscv

This commits creates the very first makefiles, directories and
subdirectories for RISC-V port. It also creates a new platform flavor
named plat

riscv: create makefiles and directories tree for riscv

This commits creates the very first makefiles, directories and
subdirectories for RISC-V port. It also creates a new platform flavor
named plat-spike. Spike is a reference functional RISC-V ISA simulator
which provides full system emulation and it is developed alongside the
RISC-V toolchain.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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