core: riscv: add plat-virt

Add Qemu Virt RISC-V platform.
Reference:
https://www.qemu.org/docs/master/system/riscv/virt.html

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: J

core: riscv: add plat-virt

Add Qemu Virt RISC-V platform.
Reference:
https://www.qemu.org/docs/master/system/riscv/virt.html

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: provide delay_arch.h

Implement timeout_init_us() and timeout_elapsed().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@lin

core: riscv: provide delay_arch.h

Implement timeout_init_us() and timeout_elapsed().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: add time source based on time registers

Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode
and CLINT MTIME register for M-Mode.
CFG_RISCV_TIME_SOURCE_RDTIME flag to

core: riscv: add time source based on time registers

Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode
and CLINT MTIME register for M-Mode.
CFG_RISCV_TIME_SOURCE_RDTIME flag to enable or not building the time
source. CFG_RISCV_MTIME_RATE defines the timer rate, default to 10MHz.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide <kernel/time.h>

Add read_time() function to get time based on CSR_TIME
and CSR_HTIME registers for S-Mode and CLINT MTIME register
for M-Mode.

Signed-off-by: Marouene Boubakri

core: riscv: provide <kernel/time.h>

Add read_time() function to get time based on CSR_TIME
and CSR_HTIME registers for S-Mode and CLINT MTIME register
for M-Mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: implement core local interruptor (clint) driver

An initial implementation of RISC-V CLINT driver with MTIMER
device to provide machine-level timer functionality.

Signed-off-by: Marouen

core: riscv: implement core local interruptor (clint) driver

An initial implementation of RISC-V CLINT driver with MTIMER
device to provide machine-level timer functionality.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide kern.ld.S

Provide script to allow linking OP-TEE core for RISC-V.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linar

core: riscv: provide kern.ld.S

Provide script to allow linking OP-TEE core for RISC-V.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv.mk: add mm and tee subdirectories to build tree

Add mm and tee subdirectories to core-platform-subdirs.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by:

core: riscv: riscv.mk: add mm and tee subdirectories to build tree

Add mm and tee subdirectories to core-platform-subdirs.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: kernel: provide link.mk

Link and generate tee.(elf,bin,dmp,map,symb_sizes).

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@lin

core: riscv: kernel: provide link.mk

Link and generate tee.(elf,bin,dmp,map,symb_sizes).

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: include: riscv.h: define generic CSR registers

To allow reading/writing CSR registers regardless the privilege mode
selected to build and boot OP-TEE OS.

Signed-off-by: Marouene Boubakri <ma

riscv: include: riscv.h: define generic CSR registers

To allow reading/writing CSR registers regardless the privilege mode
selected to build and boot OP-TEE OS.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: add console driver for S-Mode using SBI

Implements a generic console driver using legacy SBI extension.
This introduces a flag CFG_RISCV_SBI_CONSOLE to decide building
the driver or n

riscv: kernel: add console driver for S-Mode using SBI

Implements a generic console driver using legacy SBI extension.
This introduces a flag CFG_RISCV_SBI_CONSOLE to decide building
the driver or not. This allows using another UART driver instead.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: sbi: add RISC-V SBI interface

Allow OP-TEE core running in S-Mode (supervisor) to interface with
Supervisor Execution Environment (SEE) through environmental calls (ecall).
Adds CFG_R

riscv: kernel: sbi: add RISC-V SBI interface

Allow OP-TEE core running in S-Mode (supervisor) to interface with
Supervisor Execution Environment (SEE) through environmental calls (ecall).
Adds CFG_RISCV_SBI flag to enable or disable it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: core: riscv.mk: select privilege mode of OP-TEE core

Introduce CFG_RISCV_M_MODE and CFG_RISCV_S_MODE flags to decide
in which privilege level OP-TEE OS will run, respectively, machine mode
or

riscv: core: riscv.mk: select privilege mode of OP-TEE core

Introduce CFG_RISCV_M_MODE and CFG_RISCV_S_MODE flags to decide
in which privilege level OP-TEE OS will run, respectively, machine mode
or supervisor mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: set author to be same as Signed-off-by:]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: spinlock.S: make __cpu_spin_trylock() visible

Function __cpu_spin_trylock() is need by trace_ext.c, therefore,
do not hide it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp

riscv: kernel: spinlock.S: make __cpu_spin_trylock() visible

Function __cpu_spin_trylock() is need by trace_ext.c, therefore,
do not hide it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-spike: conf.mk: set CFG_TEE_CORE_LOG_LEVEL to default

Do not force CFG_TEE_CORE_LOG_LEVEL to zero in
core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubak

riscv: plat-spike: conf.mk: set CFG_TEE_CORE_LOG_LEVEL to default

Do not force CFG_TEE_CORE_LOG_LEVEL to zero in
core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: mm: tlb_helpers_rv.S: translation look-aside buffer invalidate

Implement tlbi_all(), tlbi_mva_allasid() and tlbi_asid() using supervisor
memory-management fence instruction SFENCE.VMA.

Signe

riscv: mm: tlb_helpers_rv.S: translation look-aside buffer invalidate

Implement tlbi_all(), tlbi_mva_allasid() and tlbi_asid() using supervisor
memory-management fence instruction SFENCE.VMA.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-spike: conf.mk: set CFG_TEE_RAM_VA_SIZE to 4MB

Set CFG_TEE_RAM_VA_SIZE to 0x00400000 in core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
A

riscv: plat-spike: conf.mk: set CFG_TEE_RAM_VA_SIZE to 4MB

Set CFG_TEE_RAM_VA_SIZE to 0x00400000 in core/arch/riscv/plat-spike/conf.mk

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: include: riscv_macros.S: define RISC-V macro helpers

Add multiplication macro for RISC-V harts without M extension.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jer

riscv: include: riscv_macros.S: define RISC-V macro helpers

Add multiplication macro for RISC-V harts without M extension.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: add stub for tee_time_get_sys_time()

A stub implementation which returns TEE_ERROR_NOT_IMPLEMENTED for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jen

riscv: kernel: add stub for tee_time_get_sys_time()

A stub implementation which returns TEE_ERROR_NOT_IMPLEMENTED for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: kernel: idle.c: implement cpu_idle()

Required by panic() to abort current execution. It ensures memory
operations were complete and stalls the hart.

Signed-off-by: Marouene Boubakri <marouen

riscv: kernel: idle.c: implement cpu_idle()

Required by panic() to abort current execution. It ensures memory
operations were complete and stalls the hart.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: kernel: main.c: implement tee_otp_get_hw_unique_key()

Sets the hardware unique key to zero. To model OTP device, Spike introduce
the ability to write plugins in the form of shared object file

riscv: kernel: main.c: implement tee_otp_get_hw_unique_key()

Sets the hardware unique key to zero. To model OTP device, Spike introduce
the ability to write plugins in the form of shared object files that allow
user-defined Memory-Mapped-I/O behaviors.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: include: add core_mmu_arch.h

Add defines for MMU configuration and helper functions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere

riscv: include: add core_mmu_arch.h

Add defines for MMU configuration and helper functions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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riscv: include: add thread_arch.h

Minimalist version which defines contexts registers structures and
thread local structure. This to allow compiling for RISC-V architecture.

Signed-off-by: Marouene

riscv: include: add thread_arch.h

Minimalist version which defines contexts registers structures and
thread local structure. This to allow compiling for RISC-V architecture.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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riscv: include: add cache_helpers_arch.h

Nothing to define for now.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

riscv: core: define CFG_MAX_CACHE_LINE_SHIFT in riscv.mk

Define platform specific maximum cache line size in address lines.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Je

riscv: core: define CFG_MAX_CACHE_LINE_SHIFT in riscv.mk

Define platform specific maximum cache line size in address lines.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: include: kernel: add tee_l2cc_mutex.h

The tee_l2cc_mutex.h header file is required by core/mm/core_mmu.c
and core/mm/vm.c, therefore, add an empty one to pass compilation.

Signed-off-by: Mar

riscv: include: kernel: add tee_l2cc_mutex.h

The tee_l2cc_mutex.h header file is required by core/mm/core_mmu.c
and core/mm/vm.c, therefore, add an empty one to pass compilation.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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