core: riscv: kernel: Fix stack pointer initialization for each hart

The RISC-V privileged specification defines that at least one hart must
have a hart ID of zero. Since at least one stack_tmp_strid

core: riscv: kernel: Fix stack pointer initialization for each hart

The RISC-V privileged specification defines that at least one hart must
have a hart ID of zero. Since at least one stack_tmp_stride is required
for calculating the initial SP value for each hart, the formula should
be address of stack_tmp plus (hartid+1) multiplied by stack_tmp_stride.

This commit fixes the formula for initializing SP of each hart,
otherwise the stack underflow happens to hart 0.

Fixes: 93e54a63925f ("riscv: kernel: entry.S: provide entry script")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Refactor macros for inline assembly of CSR operations

Current CSR macros with inline assembly will lead to compilation error,
because they use pre-processor stringizing not value substi

core: riscv: Refactor macros for inline assembly of CSR operations

Current CSR macros with inline assembly will lead to compilation error,
because they use pre-processor stringizing not value substitution. The
definitions such as CSR_XSTATUS are not sustituted to CSR encoding in
CSR macros and compiler generates: Error: unknown CSR `CSR_XSTATUS'.

This patch fixes it by making the given CSR to be an assembly input
operand with constraint "i", which is used to indicate the operand is
an immediate integer operand. Thus, the CSR encoding can be correctly
compiled.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: mm: Add missing return for TLB helpers

These functions should contain tailing ret instruction to return to
caller.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome F

core: riscv: mm: Add missing return for TLB helpers

These functions should contain tailing ret instruction to return to
caller.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: kernel: Fix compilation error with missing parameter

This patch adds "unsigned long tos_fw_config" as second parameter for
RISC-V's boot_init_primary_late() to solve compilation error.

core: riscv: kernel: Fix compilation error with missing parameter

This patch adds "unsigned long tos_fw_config" as second parameter for
RISC-V's boot_init_primary_late() to solve compilation error.

Fixes: 809fa817ae63 ("core: ffa: add TOS_FW_CONFIG handling")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: remove TEE_RAM_VA_START and TEE_TEXT_VA_START

TEE_RAM_VA_START and TEE_TEXT_VA_START are defined to exactly the same
thing as TEE_RAM_START and TEE_LOAD_ADDR respectively. They don't deal
with

core: remove TEE_RAM_VA_START and TEE_TEXT_VA_START

TEE_RAM_VA_START and TEE_TEXT_VA_START are defined to exactly the same
thing as TEE_RAM_START and TEE_LOAD_ADDR respectively. They don't deal
with virtual addresses as the names suggests, they too represent
physical addresses. So remove TEE_RAM_VA_START and TEE_TEXT_VA_START to
get rid of some redundancy.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: rename load_offset in struct core_mmu_config

Renames the field load_offset in struct core_mmu_config to the more
accurate name map_offset.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro

core: rename load_offset in struct core_mmu_config

Renames the field load_offset in struct core_mmu_config to the more
accurate name map_offset.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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virt: rename CFG_VIRTUALIZATION to CFG_NS_VIRTUALIZATION

With the advent of virtualization support at S-EL2 in the Armv8.4-A
architecture, CFG_VIRTUALIZATION has become ambiguous. Let's rename
it to

virt: rename CFG_VIRTUALIZATION to CFG_NS_VIRTUALIZATION

With the advent of virtualization support at S-EL2 in the Armv8.4-A
architecture, CFG_VIRTUALIZATION has become ambiguous. Let's rename
it to CFG_NS_VIRTUALIZATION to indicate more clearly that it is about
supporting virtualization on the non-secure side.

This commit is the result of the following command:

$ for f in $(git grep -l -w CFG_VIRTUALIZATION); do \
sed -i -e 's/CFG_VIRTUALIZATION/CFG_NS_VIRTUALIZATION/g' $f; \
done

...plus the compatibility line in mk/config.mk:

CFG_NS_VIRTUALIZATION ?= $(CFG_VIRTUALIZATION)

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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core: riscv: provide cache_helpers_rv.S

Simple implementation of instruction cache and data cache operations
that relies on RISC-V's fence and fence.i instructions.

Signed-off-by: Marouene Boubakri

core: riscv: provide cache_helpers_rv.S

Simple implementation of instruction cache and data cache operations
that relies on RISC-V's fence and fence.i instructions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide arch_scall_rv.S

Provide an implementation of scall_do_call(), syscall_sys_return()
and syscall_panic().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: J

core: riscv: provide arch_scall_rv.S

Provide an implementation of scall_do_call(), syscall_sys_return()
and syscall_panic().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: arch_scall.c: implement scall_save_panic_stack()

Provide an implementation of scall_save_panic_stack() needed by
scall_sys_return_helper().

Signed-off-by: Marouene Boubakri <marouene.b

core: riscv: arch_scall.c: implement scall_save_panic_stack()

Provide an implementation of scall_save_panic_stack() needed by
scall_sys_return_helper().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide arch_scall.h

Specifies what registers from thread_scall_regs are used for system calls.
The syscall number is provided in t0 register. The syscall max args is
provided in t1 reg

core: riscv: provide arch_scall.h

Specifies what registers from thread_scall_regs are used for system calls.
The syscall number is provided in t0 register. The syscall max args is
provided in t1 register. The return value is provided in a0 register.
The panic and panic code are provided respectively in a1 and a2 registers.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: implement thread management routines in thread_arch.c

This commit implements an initial thread management for RISC-V. It covers
the following routines:

- Exceptions un/masking
- Trap h

core: riscv: implement thread management routines in thread_arch.c

This commit implements an initial thread management for RISC-V. It covers
the following routines:

- Exceptions un/masking
- Trap handling, including syscalls handling.
- Thread allocation, execution, suspension, freeing with slight changes
to set RISC-V registers such as CSRs.
- RPC.

Pending routines:
- Floatting point support F/D/Q/L extensions and software FP.
- Abort mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: provide abort.c

Initial implementation of abort handler for RISC-V.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: riscv: add thread manager assembly code in thread_rv.S

This commit implements:
- An entry point of trap handler in non-vectored mode.
- thread_unwind_user_mode() and thread_exit_user_mode()
to

core: riscv: add thread manager assembly code in thread_rv.S

This commit implements:
- An entry point of trap handler in non-vectored mode.
- thread_unwind_user_mode() and thread_exit_user_mode()
to return from U-Mode.
- __thread_enter_user_mode() to jump to U-Mode from S-Mode or M-Mode.
- thread_std_smc_entry(), thread_resume() and thread_rpc().

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv.h: bind registers to their ABI names

For better readability of code, allow using register ABI names
in ASM sources to match registers declarations in C files.

Signed-off-by: Maro

core: riscv: riscv.h: bind registers to their ABI names

For better readability of code, allow using register ABI names
in ASM sources to match registers declarations in C files.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: asm-defines.c: create and populate with thread-related defines

Create core/arch/riscv/kernel/asm-defines.c and add defines for thread_ctx,
thread_core_local, thread_ctx_regs, thread_use

core: riscv: asm-defines.c: create and populate with thread-related defines

Create core/arch/riscv/kernel/asm-defines.c and add defines for thread_ctx,
thread_core_local, thread_ctx_regs, thread_user_mode_rec, thread_trap_regs
and thread_scall_regs.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: kernel: add several modifications to thread_arch.h

This commits:
- Adds 4 trampoline registers to thread_core_local to store arguments of
__thread_enter_user_mode before jumping to U-Mo

core: riscv: kernel: add several modifications to thread_arch.h

This commits:
- Adds 4 trampoline registers to thread_core_local to store arguments of
__thread_enter_user_mode before jumping to U-Mode to be restored later
after exiting U-Mode.
- Populates thread_trap_regs with all registers available on RV 64/32,
this holds the trap frame for trap handling.
- Populates thread_ctx_regs with general purpose registers.
- Makes generic definition of THREAD_EXCP_FOREIGN_INTR and
THREAD_EXCP_NATIVE_INTR to work both on S-Mode and M-Mode.
- Adds prototypes for Soft FP (to be implemented later) and RPC caches.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: kernel: add thread_private_arch.h

Declares stacks sizes, thread_user_mode_rec structure to restore
context after exiting from U-Mode. It also adds prototypes for
thread_rv.s and thread_

core: riscv: kernel: add thread_private_arch.h

Declares stacks sizes, thread_user_mode_rec structure to restore
context after exiting from U-Mode. It also adds prototypes for
thread_rv.s and thread_arch.c

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv.h: define generic CSRs to handle traps

Added xSTATUS and xIE related fields and flags for traps
handling.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: J

core: riscv: riscv.h: define generic CSRs to handle traps

Added xSTATUS and xIE related fields and flags for traps
handling.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: riscv_macros.S: add load_xregs and save_xregs macros

Introduce helper macros to load/store a range registers from/to a base
register at a given offset. It uses LDR and STR macros define

core: riscv: riscv_macros.S: add load_xregs and save_xregs macros

Introduce helper macros to load/store a range registers from/to a base
register at a given offset. It uses LDR and STR macros defined in riscv.h
for respectively RV32 and RV64. Offsets are shifted by RISCV_XLEN_BYTES.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add StMM to reported services

Adds StMM to the list of services reported by the device pseudo TA.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias

core: add StMM to reported services

Adds StMM to the list of services reported by the device pseudo TA.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce scall layer from svc parts

Introduces a scall layer by renaming various thread_svc* names and
_*handle_svc() functions and function pointers as a first step in doing
architecture neu

core: introduce scall layer from svc parts

Introduces a scall layer by renaming various thread_svc* names and
_*handle_svc() functions and function pointers as a first step in doing
architecture neutral syscall processing.

The name scall is used instead of syscall since the syscall_ prefix is
reserved for the functions implementing the actual syscall. While scall
is the infrastructure used to reach the syscall functions.

No files are renamed and removed at this stage. This patch doesn't
change any behaviour.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: kernel: entry.S: provide entry script

Provide core's single entry point for RV32/RV64 in S/M Modes.
For now it performs: booting primary and secondary harts. Setting stack
pointer, thread poi

riscv: kernel: entry.S: provide entry script

Provide core's single entry point for RV32/RV64 in S/M Modes.
For now it performs: booting primary and secondary harts. Setting stack
pointer, thread pointer (to thread_core_local), supervisor address
translation and protection register, clearing BSS...etc and calls to
appropriate functions to initialize the MMU and continue to boot flow
from boot.c.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: kernel: implement boot flow in boot.c

Provide an implementation of init_tee_runtime(), plat_primary_init_early()
boot_init_primary_early(), boot_init_primary_late(), boot_init_secondary()
and

riscv: kernel: implement boot flow in boot.c

Provide an implementation of init_tee_runtime(), plat_primary_init_early()
boot_init_primary_early(), boot_init_primary_late(), boot_init_secondary()
and helper functions. For now init_sec_mon() is kept to be replaced later
by a routine to initialize SBI implementation (to for example, probe for
available SBI extensions).

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv.mk: disable unsupported configuration flags

Features which are not supported, or, specific to other
architectures are disabled.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.c

core: riscv.mk: disable unsupported configuration flags

Features which are not supported, or, specific to other
architectures are disabled.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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