riscv: mm: core_mmu_arch.h: define translation levels parameters

This commits modify core_mmu_arch.h to:
- Set CORE_MMU_PGDIR_LEVEL to zero, since the deepest translation
level is always zero.
- Set

riscv: mm: core_mmu_arch.h: define translation levels parameters

This commits modify core_mmu_arch.h to:
- Set CORE_MMU_PGDIR_LEVEL to zero, since the deepest translation
level is always zero.
- Set CORE_MMU_BASE_TABLE_LEVEL to (RISCV_PGLEVELS - 1) which the first
translation level depending on the MMU mode.
- Set RISCV_MMU_ASID_WIDTH to number of bits used to represent ASID.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Add external DT initialization and updating

Initialize the external DT which is provided by early boot stage. The
external DT is updated by adding reserved-memory node for secure RAM.

core: riscv: Add external DT initialization and updating

Initialize the external DT which is provided by early boot stage. The
external DT is updated by adding reserved-memory node for secure RAM.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Get external device tree provided by early boot stage

Early boot stage (i.e., M-mode firmware) can provide external device
tree via register a1. Implement code that OP-TEE gets device t

core: riscv: Get external device tree provided by early boot stage

Early boot stage (i.e., M-mode firmware) can provide external device
tree via register a1. Implement code that OP-TEE gets device tree from
a1 and saves the value into s1 for future use. Platform can also define
CFG_DT_ADDR to forcely set the physical address of the device tree.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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arm64: Introduce permissive PAN implementation

Privileged Access Never (PAN) is a part of ARMv8.1 extension that
restricts accesses to unprivileged memory from privileged mode
in order to prevent un

arm64: Introduce permissive PAN implementation

Privileged Access Never (PAN) is a part of ARMv8.1 extension that
restricts accesses to unprivileged memory from privileged mode
in order to prevent unintended accesses to potentially malicious
memory.

This introduces configuration of PAN and helper functions
enter_user_access() and exit_user_access() that toggles PSTATE.PAN
that controls the behavior of PAN.

Current OP-TEE impelmentation is not ready to apply strict PAN policy
due to missing user-access function uses, etc.

Hence, this patch takes a very permissive approach (yet better
than nothing), where PAN is deactivated in the entire lifetime of
thread_svc_handler (i.e., system call).

Signed-off-by: Seonghyun Park <seonghp@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Add TLB operation related to virtual address and ASID

Add TLB invalidate function which is corresponding to virtual address
and ASID. The commit also adds missing declaration of tlbi_va

core: riscv: Add TLB operation related to virtual address and ASID

Add TLB invalidate function which is corresponding to virtual address
and ASID. The commit also adds missing declaration of tlbi_va_allasid().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Add cflags for excluding source files from ftrace

Some C source files may lead to incorrect behaviors in ftrace. Exclude
them when the system is compiled with ftrace support.

Signed-of

core: riscv: Add cflags for excluding source files from ftrace

Some C source files may lead to incorrect behaviors in ftrace. Exclude
them when the system is compiled with ftrace support.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Implement timer related functions for ftrace support

Implement barrier_read_counter_timer() to read the timer value after a
barrier. Implement read_cntfrq() to get the frequency of mach

core: riscv: Implement timer related functions for ftrace support

Implement barrier_read_counter_timer() to read the timer value after a
barrier. Implement read_cntfrq() to get the frequency of machine timer
counter. The read_time() is moved from header to C source file to reduce
the code size.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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libutils: Add riscv.S to make it available for core and TA libs

Some assembly macros are necessary for both OP-TEE core and TA
libraries. Therefore, we add riscv specific assembly file into libutils

libutils: Add riscv.S to make it available for core and TA libs

Some assembly macros are necessary for both OP-TEE core and TA
libraries. Therefore, we add riscv specific assembly file into libutils
and move some assembly related macros from riscv.h to riscv.S.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Use standard ABI Mnemonic for frame pointer

Some older toolchain might not recognize "fp". To fix it, we use
standard ABI Mnemonic "s0" instead of "fp".

Signed-off-by: Alvin Chang <alv

core: riscv: Use standard ABI Mnemonic for frame pointer

Some older toolchain might not recognize "fp". To fix it, we use
standard ABI Mnemonic "s0" instead of "fp".

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Update saving panic registers from _utee_panic()

The _utee_panic() function only saves ra and s0(fp) onto stack. So we
only get them from the stack and save them as epc and s0 as abort

core: riscv: Update saving panic registers from _utee_panic()

The _utee_panic() function only saves ra and s0(fp) onto stack. So we
only get them from the stack and save them as epc and s0 as abort
registers.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Add TA compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable

core: riscv: Add TA compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable
the CFG_UNWIND to let compiler not to omit the frame pointer when it
builds TA.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename

core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename "mva" to common terminology, such as "va". This PR renames "mva"
to "va" in TLB operations for ARM64 and RISC-V. For ARM32, "mva" is
reserved because it is really defined in ARM32's documentations.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: Introduce core_mmu_level_in_range()

Since the checking of the valid translation level is architecture
specific, the core_mmu_level_in_range() is introduced and every
architecture could imp

core: mm: Introduce core_mmu_level_in_range()

Since the checking of the valid translation level is architecture
specific, the core_mmu_level_in_range() is introduced and every
architecture could implement the function with their own translation
rules.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Fix misuse of cppflags

The -mxxx and -Wxxx are not preprocessor flags. Fix it by defining them
as C flags.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Foriss

core: riscv: Fix misuse of cppflags

The -mxxx and -Wxxx are not preprocessor flags. Fix it by defining them
as C flags.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Implement function to print kernel stack

Implement the function to print the kernel stack. The code is referenced
from ARM architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.c

core: riscv: Implement function to print kernel stack

Implement the function to print the kernel stack. The code is referenced
from ARM architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Add read_fp() and read_pc()

Implement inline functions to read PC and FP. This is required to trace
back the kernel stack.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by:

core: riscv: Add read_fp() and read_pc()

Implement inline functions to read PC and FP. This is required to trace
back the kernel stack.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Update the kernel mode unwinding

The data structure for RISC-V does not have sp, remove it in the
function. Also the function and structure are renamed.

Signed-off-by: Alvin Chang <alv

core: riscv: Update the kernel mode unwinding

The data structure for RISC-V does not have sp, remove it in the
function. Also the function and structure are renamed.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Add core compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enab

core: riscv: Add core compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable
the CFG_UNWIND to let compiler not to omit the frame pointer.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Save and restore register s0 when trap occurs

In RISC-V the frame pointer is stored into register s0. It is necessary
to save/restore s0 when we enable CFG_UNWIND to process stack unwin

core: riscv: Save and restore register s0 when trap occurs

In RISC-V the frame pointer is stored into register s0. It is necessary
to save/restore s0 when we enable CFG_UNWIND to process stack unwinding.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Correct sp before boot_init_primary_late()

Fix the stack pointer according to mentioned commits. The sp should be
assigned as thread#0's stack pointer, and the flag that indicates usage

core: riscv: Correct sp before boot_init_primary_late()

Fix the stack pointer according to mentioned commits. The sp should be
assigned as thread#0's stack pointer, and the flag that indicates usage
of the temporary stack must be cleared before boot_init_primary_late()
is called. After boot_init_primary_late() is returned, we restore the
previous sp and set the flag again.

Fixes: 59ac3801b756 ("core: split boot_init_primary()")
Fixes: 1d88c0c03f3b ("core: clear temporary stack flag before entering boot_init_primary_late()")'
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: fix interrupt_main_handler() reference

Fixes itr_core_handler() reference in RiscV architecture that was renamed
interrupt_main_handler() in commit referred below.

Fixes: 358bf47c0612

core: riscv: fix interrupt_main_handler() reference

Fixes itr_core_handler() reference in RiscV architecture that was renamed
interrupt_main_handler() in commit referred below.

Fixes: 358bf47c0612 ("core: interrupt: rename itr_core_handler()")
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain s

riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain so that toolchain can generate the code correctly, these
ISA extensions should be encoded into "-march" flag. This patch
overrides the default ISA extensions which is defined in riscv.mk
to specify the extension that the platform really supports.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Add default variables for platform ISA, ABI and code model

In RISC-V, each platform may have different supported ISA extensions,
ABI, and code model. In this commit, we define the defau

core: riscv: Add default variables for platform ISA, ABI and code model

In RISC-V, each platform may have different supported ISA extensions,
ABI, and code model. In this commit, we define the default variables
of ISA extensions, ABI, and code model in RISC-V core Makefile. The
platform can further overrides the values in their plat-*/conf.mk.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <je

core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("

core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("core: split core/arch/arm/kernel/thread.c")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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