core: riscv: Fix condition of is_from_user()

RISC-V defines that xPP(previous privilege mode) field of CSR status
indicates the previous privilege level prior to the trap. Since the
encoding of user

core: riscv: Fix condition of is_from_user()

RISC-V defines that xPP(previous privilege mode) field of CSR status
indicates the previous privilege level prior to the trap. Since the
encoding of user mode is 0, we should compare the xPP field with 0 here
to know that the trap is from user mode.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x6

riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x600000,
and the number of interrupt sources should be 95.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
f

drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
file. With this change, the PLIC initialization functions no more get
the controller data as input argument. Platforms do not need to care
about the interrupt controller data instance.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: tee: add entry_fast.c

This commit adds an implementation of fast call handers. It copies
the original implementation replacing thread_smc_args structures
with thread_abi_args counterpar

core: riscv: tee: add entry_fast.c

This commit adds an implementation of fast call handers. It copies
the original implementation replacing thread_smc_args structures
with thread_abi_args counterparts. tee_entry_fastcall_l2cc_mutex()
has been modified to return OPTEE_ABI_RETURN_UNKNOWN_FUNCTION.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: add thread_optee_abi.c

This commit just copies thread_optee_smc.c from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alv

core: riscv: add thread_optee_abi.c

This commit just copies thread_optee_smc.c from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/teeabi_opteed_macros.h

This commit just copies teesmc_opteed_macros.h from ARM and renames
smc/SMC to abi/ABI.
All unused and ARM-related macros are removed.

Signed-of

core: riscv: include: add tee/teeabi_opteed_macros.h

This commit just copies teesmc_opteed_macros.h from ARM and renames
smc/SMC to abi/ABI.
All unused and ARM-related macros are removed.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/teeabi_opteed.h

This commit just copies teesmc_opteed.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-

core: riscv: include: add tee/teeabi_opteed.h

This commit just copies teesmc_opteed.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/optee_abi.h

This commit just copies optee_smc.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvi

core: riscv: include: add tee/optee_abi.h

This commit just copies optee_smc.h from ARM and renames
smc/SMC to abi/ABI.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: add tee/entry_fast.h

This commit just copies entry_fast.h from ARM and renames
thread_smc_args to thread_abi_args.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>

core: riscv: include: add tee/entry_fast.h

This commit just copies entry_fast.h from ARM and renames
thread_smc_args to thread_abi_args.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S

This commits moves the following functions from thread_rv.S to a separate
file thread_optee_abi_rv.S:

- thread_return_fr

core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S

This commits moves the following functions from thread_rv.S to a separate
file thread_optee_abi_rv.S:

- thread_return_from_nsec_call()
- thread_std_smc_entry() -> renamed to thread_std_abi_entry()
- thread_rpc()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure

SMC is an ARM-related keyword, make use thread_std_abi_entry instead of
thread_std_smc_entry.

Signed-off-by: Marouene Bouba

core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure

SMC is an ARM-related keyword, make use thread_std_abi_entry instead of
thread_std_smc_entry.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_private_arch.h: add std and fast calls prototypes

This commit adds the following prototypes to thread_private_arch.h:
- thread_std_abi_entry()
- __thread_std_abi_entry()
- thread

core: riscv: thread_private_arch.h: add std and fast calls prototypes

This commit adds the following prototypes to thread_private_arch.h:
- thread_std_abi_entry()
- __thread_std_abi_entry()
- thread_handle_fast_abi()
- thread_handle_std_abi()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args

SMC is an ARM-related keyword referring to Secure Monitor Call.
This commit renames thread_smc_args to thread_abi_args in
thread

core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args

SMC is an ARM-related keyword referring to Secure Monitor Call.
This commit renames thread_smc_args to thread_abi_args in
thread_arch.h and keeps the same members to guarantee compatibility
with the existing secure and non-secure domain communication protocol.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: Add definitions of CLINT for platform spike

Add definitions for base address of CLINT, otherwise build failure
occurs for platform spike.

Signed-off-by: Alvin Chang <alvinga@andestech.

core: riscv: Add definitions of CLINT for platform spike

Add definitions for base address of CLINT, otherwise build failure
occurs for platform spike.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
inclu

riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
include path of RISC-V PLIC driver header is fixed.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Load register TP from thread_user_mode_rec in trap handler

RISC-V kernel uses TP register to store thread_core_local structure.
When the thread enters user mode, the value of TP is used

core: riscv: Load register TP from thread_user_mode_rec in trap handler

RISC-V kernel uses TP register to store thread_core_local structure.
When the thread enters user mode, the value of TP is used by user mode.
Therefore, when CPU enters trap handler, it needs to restore TP to get
thread_core_local structure. In previous implementation, the value of TP
is saved under kernel SP before entering user mode, and the trap handler
restores TP from that stack location. However, the value of TP has
already been saved into the thread_user_mode_rec structure, which is
also upon kernel SP, before entering user mode. So the value of TP can
be restored just from thread_user_mode_rec, instead of saving into
another location which is under the kernel SP.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Support Privileged Access Never by CSR status.SUM bit

The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When

core: riscv: Support Privileged Access Never by CSR status.SUM bit

The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When SUM bit is
0, S-mode accesses to pages whose U bit of corresponding PTE is set will
fault. When SUM bit is 1, these accesses are permitted.

When CFG_PAN is disabled in RISC-V architecture, the status.SUM bit is
initialized as 1 by default. Therefore all accesses to user pages will
succeed. When CFG_PAN is enabled, the status.SUM bit is initialized as
0, and only set to 1 when kernel needs to access user pages.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Fix thread_rpc() wrong stack usage and CSR value

Since there are four registers to be stored onto stack, we should
preserve up to 32 bytes space on the stack instead of only 16 bytes,
o

core: riscv: Fix thread_rpc() wrong stack usage and CSR value

Since there are four registers to be stored onto stack, we should
preserve up to 32 bytes space on the stack instead of only 16 bytes,
otherwise the stack overflow occurs. The s0 is regarded as frame
pointer. The value of CSR status is also restored before returning from
thread_rpc().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Fix width of status CSR

Since we also support RV64 with 64-bit register width, fix the width of
status CSR by declaring it as "unsigned long" and encoding it by general
bit-wise operati

core: riscv: Fix width of status CSR

Since we also support RV64 with 64-bit register width, fix the width of
status CSR by declaring it as "unsigned long" and encoding it by general
bit-wise operations instead of invoking fixed-width API.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: riscv.mk: define CFG_WITH_LPAE

Set CFG_WITH_LPAE according to CFG_CORE_LARGE_PHYS_ADDR.
Memory manager makes use of CFG_WITH_LPAE, therefore, we set it
according to the platform specifi

core: riscv: riscv.mk: define CFG_WITH_LPAE

Set CFG_WITH_LPAE according to CFG_CORE_LARGE_PHYS_ADDR.
Memory manager makes use of CFG_WITH_LPAE, therefore, we set it
according to the platform specifications.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-o

core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()

main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by rena

core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()

main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by renameing to
boot_secondary_init_intc(), since interrupt controllers are always
initialized in boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: introduce primary_init_intc() and secondary_init_intc()

Rename interrupt controller initialization functions to
primary_init_intc() and secondary_init_intc(). To be called by
platform b

core: riscv: introduce primary_init_intc() and secondary_init_intc()

Rename interrupt controller initialization functions to
primary_init_intc() and secondary_init_intc(). To be called by
platform boot code to initialize interrupt controller on boot hart
and secondary harts, respectively.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: mm: initial implementation of memory management routines

An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table l

riscv: mm: initial implementation of memory management routines

An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table levels.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: kernel: asm-defines.c: add defines for struct core_mmu_config

Add CORE_MMU_CONFIG_SIZE and CORE_MMU_CONFIG_SATP defines
to asm-defines.c

Signed-off-by: Marouene Boubakri <marouene.boubakri@n

riscv: kernel: asm-defines.c: add defines for struct core_mmu_config

Add CORE_MMU_CONFIG_SIZE and CORE_MMU_CONFIG_SATP defines
to asm-defines.c

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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