core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shi

core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shift byte for differ environmnt. therefore remove the const value and
using REGOFF() macro to fit the RV32/RV64 environment.

Signed-off-by: Randolph Lin <randolph@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: kernel: spinlock.S: make __cpu_spin_trylock() visible

Function __cpu_spin_trylock() is need by trace_ext.c, therefore,
do not hide it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp

riscv: kernel: spinlock.S: make __cpu_spin_trylock() visible

Function __cpu_spin_trylock() is need by trace_ext.c, therefore,
do not hide it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ens

core: riscv: spinlock.c: implement spin-locking primitives

Implement __cpu_spin_lock(), __cpu_spin_unlock() and __cpu_spin_trylock()
Use atomic-instruction amoswap in "A" extension for locks and ensure memory
ordering using fence instruction.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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