| #
5c718542 |
| 18-Aug-2024 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Remove thread_exit_user_mode()
Currently, the user mode abort and some system calls return to kernel mode by thread_exit_user_mode(). Although this function creates a shorter path to re
core: riscv: Remove thread_exit_user_mode()
Currently, the user mode abort and some system calls return to kernel mode by thread_exit_user_mode(). Although this function creates a shorter path to return to kernel mode, it leads to some problems because the function does not update the core local flags. Especially when CFG_CORE_DEBUG_CHECK_STACKS=y, some checks will fail due to wrong type of stack recorded in the core local flags.
Fix it by removing thread_exit_user_mode(). So that the core local flags can be correctly updated in the common trap handler.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
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| #
de45f2fb |
| 23-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Apply exception return to handle_user_mode_panic()
Now thread_exit_user_mode() executes exception return to kernel mode. Invoke xstatus_for_xret() helper function to prepare CSR STATUS
core: riscv: Apply exception return to handle_user_mode_panic()
Now thread_exit_user_mode() executes exception return to kernel mode. Invoke xstatus_for_xret() helper function to prepare CSR STATUS for exception return.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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| #
b498b831 |
| 26-May-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Update the kernel mode unwinding
The data structure for RISC-V does not have sp, remove it in the function. Also the function and structure are renamed.
Signed-off-by: Alvin Chang <alv
core: riscv: Update the kernel mode unwinding
The data structure for RISC-V does not have sp, remove it in the function. Also the function and structure are renamed.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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