| #
37ad62c2 |
| 15-Jul-2025 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: sbi.h: expose sbi_ecall helper in public header
Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across individual SBI extension implementations. This prepares for modular
core: riscv: sbi.h: expose sbi_ecall helper in public header
Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across individual SBI extension implementations. This prepares for modularizing each SBI extension (e.g., HSM, MPXY) into its own file while centralizing the ecall interface.
Removes the now-duplicated inline definition from sbi.c.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
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| #
cc967d3f |
| 28-Jun-2025 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: sbi.h: add SBI_EXT_MPXY definition
Added `SBI_EXT_MPXY` (0x4D505859) as per latest RISC-V SBI extensions.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvi
core: riscv: sbi.h: add SBI_EXT_MPXY definition
Added `SBI_EXT_MPXY` (0x4D505859) as per latest RISC-V SBI extensions.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
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| #
1af87903 |
| 28-Jun-2025 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: sbi.h: extend SBI error codes
Add more SBI error codes to synchronize with SBI specification.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alv
core: riscv: sbi.h: extend SBI error codes
Add more SBI error codes to synchronize with SBI specification.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
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| #
72fc7d74 |
| 12-Jan-2025 |
Yu-Chien Peter Lin <peter.lin@sifive.com> |
riscv: kernel: sbi: introduce sbi_hsm_hart_get_status() function
Introduce sbi_hsm_hart_get_status() function and add comment for sbi_hsm_hart_start().
Signed-off-by: Yu-Chien Peter Lin <peter.lin@
riscv: kernel: sbi: introduce sbi_hsm_hart_get_status() function
Introduce sbi_hsm_hart_get_status() function and add comment for sbi_hsm_hart_start().
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
d1c9f59a |
| 03-Feb-2024 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: sbi_console: prefer SBI v2.0 DBCN ecall over legacy sbi_console_putchar()
As the legacy sbi_console_putchar() may be deprecated in the future, it is recommended to use sbi_dbcn_write_byte() p
riscv: sbi_console: prefer SBI v2.0 DBCN ecall over legacy sbi_console_putchar()
As the legacy sbi_console_putchar() may be deprecated in the future, it is recommended to use sbi_dbcn_write_byte() provided by SBI v2.0 DBCN extension [1]. However, if the DBCN extension is not supported, sbi_console_putchar() can still be used as the last resort.
Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/v2.0/src/ext-debug-console.adoc#function-console-write-byte-fid-2 [1] Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
2b31189c |
| 04-Mar-2024 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR
Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better readability. Also, provide a function description.
Signed-off-by:
riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR
Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better readability. Also, provide a function description.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
286e0fd9 |
| 03-Feb-2024 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: sbi: minor cleanup for SBI HSM related definitions
Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated type for function ID definition for better clarity and consistency with th
riscv: sbi: minor cleanup for SBI HSM related definitions
Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated type for function ID definition for better clarity and consistency with the following commits.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
d50fee03 |
| 16-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: prefix header file guard names with __
Improves header files guard names consistency by using a __ prefix where missing.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by:
core: prefix header file guard names with __
Improves header files guard names consistency by using a __ prefix where missing.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
0fb22936 |
| 11-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Implement SBI based protocol
Rename thread_return_from_nsec_call() to thread_return_to_ree() for more general behavior, since TEE might not only be called by REE, but also do something
core: riscv: Implement SBI based protocol
Rename thread_return_from_nsec_call() to thread_return_to_ree() for more general behavior, since TEE might not only be called by REE, but also do something on its own initiative (e.g., handle secure interrupts).
This commit also implements SBI based protocol used to return control to REE. The register a7 encodes SBI TEE extension ID, which is temporarily defined here. We may have ratified SBI TEE extension in the future and we can apply ratified ID at that time. The register a6 is unused and encoded as 0. The returned arguments are encoded into registers a0~a5 and should be provided by the caller.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
3cdf0b24 |
| 11-Nov-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: kernel: sbi: add RISC-V SBI interface
Allow OP-TEE core running in S-Mode (supervisor) to interface with Supervisor Execution Environment (SEE) through environmental calls (ecall). Adds CFG_R
riscv: kernel: sbi: add RISC-V SBI interface
Allow OP-TEE core running in S-Mode (supervisor) to interface with Supervisor Execution Environment (SEE) through environmental calls (ecall). Adds CFG_RISCV_SBI flag to enable or disable it.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> [jf: set author to be same as Signed-off-by:] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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