core: arm: ffa: optionally use CFG_CORE_ASYNC_NOTIF_GIC_INTID

Allow an FF-A configuration to optionally use
CFG_CORE_ASYNC_NOTIF_GIC_INTID to configure the interrupt used to notify
the normal world

core: arm: ffa: optionally use CFG_CORE_ASYNC_NOTIF_GIC_INTID

Allow an FF-A configuration to optionally use
CFG_CORE_ASYNC_NOTIF_GIC_INTID to configure the interrupt used to notify
the normal world that there are pending notifications. For FF-A
CFG_CORE_ASYNC_NOTIF_GIC_INTID is only dealt with in platform code so
relax the static assert about interrupt IDs in (the unused)
add_optee_dt_node().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: enable nvmem support

Enable nvmem support to allow reading hardware unique key from the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thoma

plat-sam: enable nvmem support

Enable nvmem support to allow reading hardware unique key from the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: sama5d2: add sfc node for the secure fuse controller

Add the definition of the atmel_sfc controller in the sama5d2 device-tree.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-

dts: sama5d2: add sfc node for the secure fuse controller

Add the definition of the atmel_sfc controller in the sama5d2 device-tree.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: Clear FFA_MEM_RETRIEVE_RESP memory descriptor fields

Clear the memory descriptors in FFA_MEM_RETRIEVE_RESP calls in order to
set the reserved fields to zero. The caller might check if the

core: ffa: Clear FFA_MEM_RETRIEVE_RESP memory descriptor fields

Clear the memory descriptors in FFA_MEM_RETRIEVE_RESP calls in order to
set the reserved fields to zero. The caller might check if the reserved
fields are zero as it is stated in the FF-A spec. With FF-A v1.1 the
memory transaction descriptor's 4 byte field at offset 24 has changed
from reserved (MBZ) to Endpoint memory access descriptor size
(non-zero). With the reserved field not cleared in the v1.0 descriptor,
the caller cannot verify if it got the right version of the memory
transaction descriptor.

This issue only affects the FFA_MEM_RETRIEVE_RESP call at the
S-EL1 <-> S-EL0 interface, in all other cases the descriptors are
cleared properly.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: allow cache_op_outer() to operate on non-secure buffers

According the ARM PL310 documentation, if the operation is specific
to the PA, the behavior is presented in the following manner:

core: arm: allow cache_op_outer() to operate on non-secure buffers

According the ARM PL310 documentation, if the operation is specific
to the PA, the behavior is presented in the following manner:
- Secure access: The data in the cache is only affected by the
the operation if it is secure.
- Non-secure access: The data in the cache is only affected by the
operation if it is non-secure.

Depending on the buffer location, use the secure or non-secure PL310
base address to do physical address based cache operation on the
buffer.

Link: https://developer.arm.com/documentation/ddi0246/a/programmer-s-model/register-descriptions/register-7--cache-maintenance-operations
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat: imx: implement pl310_nsbase()

Map PL310 registers as non-secure.
Implement pl310_nsbase() that returns non-secure PL310 base address.

Signed-off-by: Clement Faure <clement.faure@nxp.com

core: plat: imx: implement pl310_nsbase()

Map PL310 registers as non-secure.
Implement pl310_nsbase() that returns non-secure PL310 base address.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add pl310_nsbase() function

Add pl310_nsbase() function to return non-secure PL310 base address.

The default implementation is a weak function that returns the secure
PL310 base address to ma

core: add pl310_nsbase() function

Add pl310_nsbase() function to return non-secure PL310 base address.

The default implementation is a weak function that returns the secure
PL310 base address to match the previous behavior where only the secure
base address was returned.

It is up to the platform to implement that function.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: sa2ul_rng: check if rng is enabled before to do a read

Check if rng is enabled in sa2ul_rng_read128(), if not the
initialization sequence is run.
After a suspend to ram, the rng may be in r

plat-k3: sa2ul_rng: check if rng is enabled before to do a read

Check if rng is enabled in sa2ul_rng_read128(), if not the
initialization sequence is run.
After a suspend to ram, the rng may be in reset state, and it has to be
re-initialized if in reset state.

Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: read_64bit_pair()

Implement read_64bit_pair that read two 64 bits data together.

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-sam: force CFG_EXTERNAL_DT to n

Because this feature isn't used on SAM platforms and to disable DT
insecure warning.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jens Wik

plat-sam: force CFG_EXTERNAL_DT to n

Because this feature isn't used on SAM platforms and to disable DT
insecure warning.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: secure pins for peripherals used in the secure world

These pins are used by RCC MCO and the I2C4. As these peripherals are
used in OP-TEE, secure them.

Signed-off-by: Gatien Chevallier

dts: stm32: secure pins for peripherals used in the secure world

These pins are used by RCC MCO and the I2C4. As these peripherals are
used in OP-TEE, secure them.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: fix test on CFG_STM32_UART

Fix test directive on CFG_STM32_UART that boolean CFG_ configuration
switches do not have a meaningful value.

Fixes: bd1fffe512ce ("plat-stm32mp2: add new

plat-stm32mp2: fix test on CFG_STM32_UART

Fix test directive on CFG_STM32_UART that boolean CFG_ configuration
switches do not have a meaningful value.

Fixes: bd1fffe512ce ("plat-stm32mp2: add new platform support")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: kernel_spmc: correct CFG_SECURE_PARTITION test

Replace occurrences of #if CFG_SECURE_PARTITION to a #ifdef test
as boolean CFG_ configuration switches do not have a meaningful value.

Fix

core: arm: kernel_spmc: correct CFG_SECURE_PARTITION test

Replace occurrences of #if CFG_SECURE_PARTITION to a #ifdef test
as boolean CFG_ configuration switches do not have a meaningful value.

Fixes: 4d0288475267 ("core: spmc: handle non-secure interrupts")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: add the header file for sama7g5

Include <sama7g5.h> in platform_config.h and add definitions to adapt
names already used by sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked

plat-sam: add the header file for sama7g5

Include <sama7g5.h> in platform_config.h and add definitions to adapt
names already used by sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: matrix: update code to be reuseable for sama7g5

Besides sama5d2, sama7g5 also has the matrix. Following changes are done
to make the code reuseable for supporting sama7g5:
- move definitio

plat-sam: matrix: update code to be reuseable for sama7g5

Besides sama5d2, sama7g5 also has the matrix. Following changes are done
to make the code reuseable for supporting sama7g5:
- move definition of "peri_security_array[]" from matrix.c to main.c
- replace "matrix32_base()" and "matrix64_base()" with "matrix_base()"
- update code according to the above changes

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: add stm32mp15*-scmi.dts files for when RCC is secure

For legacy reason and compatibility with existing platforms embedding
OP-TEE with RCC secure hardening being disabled, introduce -scmi.dts f

dts: add stm32mp15*-scmi.dts files for when RCC is secure

For legacy reason and compatibility with existing platforms embedding
OP-TEE with RCC secure hardening being disabled, introduce -scmi.dts for
the 4 ST boards STM32MP15x: DK1, DK2, ED1 and EV1 where we enable RCC
security require non-secure world to use SCMI resources. Add platform
flavors 157x_XXX_SCMI to ease DTS selection.

stm32mp15*-<board>.dts applies an insecure RCC configuration.
stm32mp15*-<board>-scmi.dts applies the secure RCC configuration.
This better reflects the configurations supported in the Linux kernel
and U-Boot source trees.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: update m4_rproc to support the remoteproc OP-TEE framework

Update device tree to support the load of the remoteproc firmware
by OP-TEE.
- declare m_ipc_shm memory region that can contain

dts: stm32: update m4_rproc to support the remoteproc OP-TEE framework

Update device tree to support the load of the remoteproc firmware
by OP-TEE.
- declare m_ipc_shm memory region that can contain the remote processor
resource table and trace buffer,
- update reset to align declaration with the Linux devicetree

To enable the load of the coprocessor firmware by OP-TEE, user have
to update the m4_rproc node compatible property:
-"st,stm32mp1-m4": the load is managed by Linux or U-boot,
-"st,stm32mp1-m4-tee": the load is managed by OP-TEE.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: Add the remoteproc TA in early TA list

On the stm32mp1 platform, it is possible to load firmware during the
bootloader stage, for instance, by U-boot. To enable this feature,
The remo

plat-stm32mp1: Add the remoteproc TA in early TA list

On the stm32mp1 platform, it is possible to load firmware during the
bootloader stage, for instance, by U-boot. To enable this feature,
The remoteproc TA should be added to the list of early-TAs.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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pta: stm32mp: add new remoteproc PTA

Add remoteproc PTA for the stm32mp1 platform.
The PTA relies on the stm32_remoteproc driver for the remoteproc
management.
It is charge of providing interface fo

pta: stm32mp: add new remoteproc PTA

Add remoteproc PTA for the stm32mp1 platform.
The PTA relies on the stm32_remoteproc driver for the remoteproc
management.
It is charge of providing interface for authenticating firmware images
and managing the remote processor live cycle.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Add stm32mp1 remoteproc driver

This driver is responsible for configuring the registers and memories of
the remote processor.
- It stores information about memories assigned to the remote p

drivers: Add stm32mp1 remoteproc driver

This driver is responsible for configuring the registers and memories of
the remote processor.
- It stores information about memories assigned to the remote processor
based on the device tree.
- It ensures consistency between the registered memory and the addresses
of the firmware segments to be loaded.
- Additionally, it is responsible for starting and stopping the remote
processor core.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-zynq7k: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-ti: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Andrew Davis <afd@ti.com>

plat-sunxi: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-stm: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etien

plat-stm: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <

plat-stm32mp2: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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