History log of /optee_os/core/arch/arm/ (Results 2751 – 2775 of 3635)
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7fe98f9016-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

hikey{,960}: CFG_HWSUPP_PMULL=y

Takes full advantage of LTC GHASH acceleration by using the pmull
instruction.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander

hikey{,960}: CFG_HWSUPP_PMULL=y

Takes full advantage of LTC GHASH acceleration by using the pmull
instruction.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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f6e4d9f716-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: import GHASH acceleration routines

Imports assembly code for accelerated GHASH computations and provides an
interface for using these low level functions.

The assembly code relies on features

core: import GHASH acceleration routines

Imports assembly code for accelerated GHASH computations and provides an
interface for using these low level functions.

The assembly code relies on features now available in all ARM cores. No
assembly code is enabled at all unless CFG_CRYPTO_WITH_CE = y. Code
using the PMULL/PMULL2 instruction is enabled with CFG_HWSUPP_PMULL = y.

The assembly code is written by Ard Biesheuvel
<ard.biesheuvel@linaro.org> and modified slightly here to fit better
into OP-TEE.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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685204eb16-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: io.h: add {get,put}_be{16,32,64}()

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

bdc8a29d16-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: arm64: add mov_imm assembly macro

Implement a macro mov_imm that can be used to move an immediate constant
into a 64-bit register, using between 2 and 4 movz/movk instructions
(depending on th

core: arm64: add mov_imm assembly macro

Implement a macro mov_imm that can be used to move an immediate constant
into a 64-bit register, using between 2 and 4 movz/movk instructions
(depending on the operand)

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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abaf120908-Nov-2017 Jerome Forissier <jerome.forissier@linaro.org>

Rewrite mem_usage.awk in Python

Rewrite the memory usage script in Python. No functional change, except
that the script now takes tee.elf as an argument instead of processing
the output of readelf.

Rewrite mem_usage.awk in Python

Rewrite the memory usage script in Python. No functional change, except
that the script now takes tee.elf as an argument instead of processing
the output of readelf. The makefile (make mem_usage) is adjusted
accordingly.

This makes the script shorter and easier to call, and it is now
possible to add command line options.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by Etienne Carriere <etienne.carriere@linaro.org>

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a2052c7616-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: avoid warning in wq_wake_next()

avoid:
core/arch/arm/kernel/wait_queue.c: In function 'wq_wake_next':
core/arch/arm/kernel/wait_queue.c:155:7: error: 'wake_read' may be used uninitialized in t

core: avoid warning in wq_wake_next()

avoid:
core/arch/arm/kernel/wait_queue.c: In function 'wq_wake_next':
core/arch/arm/kernel/wait_queue.c:155:7: error: 'wake_read' may be used uninitialized in this function [-Werror=maybe-uninitialized]
if (wqe->wait_read != wake_read)

When building with gcc 5.3.1

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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5209c97a14-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: pta: add PTA_INVOKE_TESTS_CMD_MUTEX

Adds test functions PTA_INVOKE_TESTS_CMD_MUTEX the invoke tests PTA
(PTA_INVOKE_TESTS_UUID). The PTA_INVOKE_TESTS_CMD_MUTEX function is used
to test in part

core: pta: add PTA_INVOKE_TESTS_CMD_MUTEX

Adds test functions PTA_INVOKE_TESTS_CMD_MUTEX the invoke tests PTA
(PTA_INVOKE_TESTS_UUID). The PTA_INVOKE_TESTS_CMD_MUTEX function is used
to test in particular read and write mutex, but also mutex over all.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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bdc1c51e14-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: extend mutex to support read locks

Extends mutex implementation to support read locks in addition to the
default lock which has write lock semantics.

With read locks multiple threads can simu

core: extend mutex to support read locks

Extends mutex implementation to support read locks in addition to the
default lock which has write lock semantics.

With read locks multiple threads can simultaneously acquire a read lock,
typically used for read only access to a shared resource.

The default mutex_lock behaves as a write lock with only a single thread
at a time able to acquire the write lock, typically used for exclusive
access to a shared resource.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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c7c4b6e314-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: allow multithreaded pseudo TAs

Introduces TA_FLAG_CONCURRENT valid for pseudo TAs only which allows
concurrent execution of the TA.

With this change a pseudo TA configured with TA_FLAG_CONCUR

core: allow multithreaded pseudo TAs

Introduces TA_FLAG_CONCURRENT valid for pseudo TAs only which allows
concurrent execution of the TA.

With this change a pseudo TA configured with TA_FLAG_CONCURRENT would
accept multiple sessions where each can be used concurrently with the
other sessions.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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1e24465f14-Nov-2017 Volodymyr Babchuk <vlad.babchuk@gmail.com>

optee: use correct type to hold exceptions state

cpu_spin_lock_xsave() returns exceptions state in uin32_t, not
in unsigned int.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-b

optee: use correct type to hold exceptions state

cpu_spin_lock_xsave() returns exceptions state in uin32_t, not
in unsigned int.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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2863328c08-Nov-2017 Pankaj Gupta <pankaj.gupta@nxp.com>

plat-ls: Add support for armv8 platform flavour

Added support for armv8 platform flavour.
- PLATFORM = ls-ls1012ardb

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sumit Garg <sum

plat-ls: Add support for armv8 platform flavour

Added support for armv8 platform flavour.
- PLATFORM = ls-ls1012ardb

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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cc45d72015-Nov-2017 Etienne Carriere <etienne.carriere@linaro.org>

core: pager can use memory between SRAM start and core load address

If core is loaded some 4kB pages above the start of the physical
internal ram, some 4kB memory block will not be used by the pager

core: pager can use memory between SRAM start and core load address

If core is loaded some 4kB pages above the start of the physical
internal ram, some 4kB memory block will not be used by the pager.

This situation can occur if the beginning of the internal ram is
used by a bootloader. Bootloader must load op-tee above its own
used memory. Such bootloader memory is freely available to op-tee
core (pager).

This change adds the physical memory between TEE RAM base address
and the op-tee entry point address to the pager page pool. This
change also default maps this area so that pager identifies physical
pages as valid page addresses.

This changes fixes the plat-vexpress against CFG_TEE_RAM_START being
different from CFG_TEE_LOAD_ADDR.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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11a9c2ba13-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: fix asan build error

Fixes the build error:
kern.ld:153: undefined symbol `__asan_shadow_start' referenced in expression

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960, G

core: fix asan build error

Fixes the build error:
kern.ld:153: undefined symbol `__asan_shadow_start' referenced in expression

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960, GP)
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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e1770e7113-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: rename to <crypto/crypto.h>

Renames core/include/tee/tee_cryp_provider.h to
core/include/crypto/crypto.h

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere

core: rename to <crypto/crypto.h>

Renames core/include/tee/tee_cryp_provider.h to
core/include/crypto/crypto.h

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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291e545010-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

Replace struct acipher_ops with function interface

Adds crypto_acipher_*() replacing struct acipher_ops in crypto_ops.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne

Replace struct acipher_ops with function interface

Adds crypto_acipher_*() replacing struct acipher_ops in crypto_ops.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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33790cc110-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

Replace struct bignum_ops with function interface

Adds crypto_bignum_*() replacing struct bignum_ops in crypto_ops.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Car

Replace struct bignum_ops with function interface

Adds crypto_bignum_*() replacing struct bignum_ops in crypto_ops.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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b887bd8f09-Nov-2017 Jens Wiklander <jens.wiklander@linaro.org>

Replace struct hash_ops with function interface

Adds crypto_hash_get_ctx_size(), crypto_hash_init(),
crypto_hash_update() and crypto_hash_final() replacing struct hash_ops
in crypto_ops.

Acked-by:

Replace struct hash_ops with function interface

Adds crypto_hash_get_ctx_size(), crypto_hash_init(),
crypto_hash_update() and crypto_hash_final() replacing struct hash_ops
in crypto_ops.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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ef86a1fe05-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: fix version-o-cflags

Fixes version-o-cflags by adding $(cflagscore) to make sure that the
address sanitizer flags are used for this object file too.

Reviewed-by: Etienne Carriere <etienne.car

core: fix version-o-cflags

Fixes version-o-cflags by adding $(cflagscore) to make sure that the
address sanitizer flags are used for this object file too.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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c10d5a5605-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

qemu_virt: fix memory configuration

Fixes memory configuration inconsistency introduced with the coherent
memory area for QEMU virt with pager enabled.

Fixes: 5402a9fe46f9 ("qemu_virt: enable smp b

qemu_virt: fix memory configuration

Fixes memory configuration inconsistency introduced with the coherent
memory area for QEMU virt with pager enabled.

Fixes: 5402a9fe46f9 ("qemu_virt: enable smp boot")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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d48df72803-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: pager: enable address sanitizer

Enables address sanitizer when pager is enabled.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@lina

core: pager: enable address sanitizer

Enables address sanitizer when pager is enabled.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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da3289a703-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: generic boot: tag paging access

When pager is enabled tag needed ranges accordingly.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@

core: generic boot: tag paging access

When pager is enabled tag needed ranges accordingly.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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626d6d1803-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: generic boot: move init_asan()

Moves the section covered by #ifdef CFG_CORE_SANITIZE_KADDRESS to above
the #ifdef CFG_WITH_PAGER section to be able to later initialize address
sanitizer with p

core: generic boot: move init_asan()

Moves the section covered by #ifdef CFG_CORE_SANITIZE_KADDRESS to above
the #ifdef CFG_WITH_PAGER section to be able to later initialize address
sanitizer with pager enabled.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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8b6814d703-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: thread: asan tag paged stacks

Tags paged stacks as accessible.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

2d227ee503-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: pager: carve out asan shadow range

Carves out address sanitizer range used for bookkeeping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wik

core: pager: carve out asan shadow range

Carves out address sanitizer range used for bookkeeping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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f16a854503-Oct-2017 Jens Wiklander <jens.wiklander@linaro.org>

core: pager: asan adoptions

Tag temporary or allocated memory ranges to allow new accesses.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander

core: pager: asan adoptions

Tag temporary or allocated memory ranges to allow new accesses.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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