linker.h: declare __data_start as non-const

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

asid: move asid allocator from tee_mmu.c to core_mmu.c

ASIDs will be allocated for individual virtrual guests, so
allocator should reside in more generic place.

Also, comment for MMU_NUM_ASIDS was

asid: move asid allocator from tee_mmu.c to core_mmu.c

ASIDs will be allocated for individual virtrual guests, so
allocator should reside in more generic place.

Also, comment for MMU_NUM_ASIDS was updated.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mmu: align va of memory regions to pa modulo PGDIR_SIZE

If pa % PGDIR_SIZE == va % PGDIR_SIZE, then we can effectively map
large smallpage-aligned regions. Most of the region can be mapped
with supe

mmu: align va of memory regions to pa modulo PGDIR_SIZE

If pa % PGDIR_SIZE == va % PGDIR_SIZE, then we can effectively map
large smallpage-aligned regions. Most of the region can be mapped
with super blocks and only ends will be mapped using small pages.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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generic_ram_layout: align TA_RAM to SMALL_PAGE_SIZE

This enables more optimal memory usage, as there will be no unused
holes in memory mappings.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail

generic_ram_layout: align TA_RAM to SMALL_PAGE_SIZE

This enables more optimal memory usage, as there will be no unused
holes in memory mappings.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: sm: initialize PMCR.DP to 1 and save/restore PMCR

Introduce CFG_SM_NO_CYCLE_COUNTING to intitialize PMCR.DP to 1 and
save/restore PMCR on world switch. Similar to what is done in ARM TF
c

core: arm: sm: initialize PMCR.DP to 1 and save/restore PMCR

Introduce CFG_SM_NO_CYCLE_COUNTING to intitialize PMCR.DP to 1 and
save/restore PMCR on world switch. Similar to what is done in ARM TF
commit 3e61b2b54336 ("Init and save / restore of PMCR_EL0 / PMCR") [1].

The purpose of this is to (hopefully) make attacks such as CLKSCREW [2]
harder to mount, although it is likely that timing information could be
obtained via other means.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Link: [1] https://github.com/ARM-software/arm-trusted-firmware/commit/3e61b2b54336
Link: [2] https://www.usenix.org/system/files/conference/usenixsecurity17/sec17-tang.pdf
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: sm: rename struct sm_mode_regs to sm_unbanked_regs

struct sm_mode_regs will soon be used to store one non-banked register
other then the mode registers (PMCR). Rename it to sm_unbanked_re

core: arm: sm: rename struct sm_mode_regs to sm_unbanked_regs

struct sm_mode_regs will soon be used to store one non-banked register
other then the mode registers (PMCR). Rename it to sm_unbanked_regs.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: make stack trace robust

Makes stack trace robust by checking addresses before copying data.
Kernel stack traces are a bit more relaxed as we have crashed already.

Reviewed-by: Jerome Forissie

core: make stack trace robust

Makes stack trace robust by checking addresses before copying data.
Kernel stack traces are a bit more relaxed as we have crashed already.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 AArch32, Aarch64)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno, QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix offset in assign_mobj_to_param_mem()

Prior to this patch assign_mobj_to_param_mem() stored the offset
supplied with a non-contiguous buffer in mem->offs. Since that offset
already is store

core: fix offset in assign_mobj_to_param_mem()

Prior to this patch assign_mobj_to_param_mem() stored the offset
supplied with a non-contiguous buffer in mem->offs. Since that offset
already is stored inside the resulting MOBJ that offset is added twice.
This patch fixes this by initializing mem->offs to 0 instead.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: update max pa after discovered nsec ddr

Once non-secure DDR is discovered either via FDT or via register_ddr()
maximum output address is updated.

Note that is only has an effect in AAr

core: arm64: update max pa after discovered nsec ddr

Once non-secure DDR is discovered either via FDT or via register_ddr()
maximum output address is updated.

Note that is only has an effect in AArch64.

Fixes: https://github.com/OP-TEE/optee_os/issues/2402
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Suggested-by: Jean-Paul Etienne <jean-paul.etienne@arm.com>
Reported-by: Rouven Czerwinski <rouven@czerwinskis.de>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64.h: add TCR_EL1_IPS_MASK

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-stm: fix MIN/MAX macro issue in platform_config.h

Use MIN_UNSAFE/MAX_UNSAFE macros as MAX/MIN macros fail to build
from in current platform_config.h imaplement with the error trace
below:

In f

plat-stm: fix MIN/MAX macro issue in platform_config.h

Use MIN_UNSAFE/MAX_UNSAFE macros as MAX/MIN macros fail to build
from in current platform_config.h imaplement with the error trace
below:

In file included from core/arch/arm/include/arm.h:8:0,
from core/arch/arm/include/kernel/thread.h:11,
from core/arch/arm/kernel/asm-defines.c:7:
lib/libutils/ext/include/util.h:24:16: error: missing binary operator before token "("
(__extension__({ __typeof__(a) _a = (a); \
^
core/arch/arm/plat-stm/./platform_config.h:190:25: note: in expansion of macro ‘MAX’
#define STM_SECDDR_END MAX(TZSRAM_BASE + TZSRAM_SIZE, \
^~~
core/arch/arm/plat-stm/./platform_config.h:204:6: note: in expansion of macro ‘STM_SECDDR_END’
#if (STM_SECDDR_END < 0x80000000ULL)
^~~~~~~~~~~~~~
make: *** [out/core/include/generated/.asm-defines.s] Error 1

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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benchmark: change the way of timestamp buffer allocation.

In case if timestamp buffer is allocated in userspace and new register
user memory API is used for its registering in OP-TEE (introduced in

benchmark: change the way of timestamp buffer allocation.

In case if timestamp buffer is allocated in userspace and new register
user memory API is used for its registering in OP-TEE (introduced in
optee_client commit 27888d73d156 ("tee_client_api: register user memory")),
there is no possibility to keep this mapping permanent among different
TEEC_InvokeCommand invocations, as all SHM are automatically unmapped from
OP-TEE VA space after TEEC_InvokeCommand is handled by OP-TEE.

Timestamp buffer is now allocated with thread_rpc_alloc_global_payload().

Fixes: https://github.com/OP-TEE/optee_os/issues/1979
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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core: support for global shared buffers

Add support of allocating SHM shared with non-secure kernel
and exported to a non-secure userspace application.

Reviewed-by: Jens Wiklander <jens.wiklander@l

core: support for global shared buffers

Add support of allocating SHM shared with non-secure kernel
and exported to a non-secure userspace application.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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plat-stm32mp1: reformat OP-TEE images to stm32 format

OP-TEE core images are reformatted into a STM32 compliant format
expected by the platform flashing tools.

Signed-off-by: Etienne Carriere <etie

plat-stm32mp1: reformat OP-TEE images to stm32 format

OP-TEE core images are reformatted into a STM32 compliant format
expected by the platform flashing tools.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: add initial support

Introduce platform stm32mp1 with board stm32mp1-stm32mp157c-ev1 based
on stm32mp1 SoC family integrating Arm Cortex-A7 technology. In its
default configuration, st

plat-stm32mp1: add initial support

Introduce platform stm32mp1 with board stm32mp1-stm32mp157c-ev1 based
on stm32mp1 SoC family integrating Arm Cortex-A7 technology. In its
default configuration, stm32mp1 OP-TEE core operates in a 256kB secure
RAM with pager support enabled.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add new RNG implementation

Adds a new cryptographically secure pseudo random number generator known
as Fortuna. The implementation is based on the description in [0]. This
implementation repla

core: add new RNG implementation

Adds a new cryptographically secure pseudo random number generator known
as Fortuna. The implementation is based on the description in [0]. This
implementation replaces the implementation in LTC which was used until
now.

Gathering of entropy has been refined with crypto_rng_add_event() to
better match how entropy is added to Fortuna. A enum crypto_rng_src
identifies the source of the event. The source also controls how the
event is added. There are two options available, queue it in a circular
buffer for later processing or adding it directly to a pool. The former
option is suitable when being called from an interrupt handler or some
other place where RPC to normal world is forbidden.

plat_prng_add_jitter_entropy_norpc() is removed and
plat_prng_add_jitter_entropy() is updated to use this new entropy source
scheme.

The configuration of LTC is simplified by this, now PRNG is always drawn
via prng_mpa_desc.

plat_rng_init() takes care of initializing the PRNG in order to allow
platforms to override or enhance the Fortuna integration.

[0] Link:https://www.schneier.com/academic/paperfiles/fortuna.pdf

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split tee_pager_init()

Splits tee_pager_init() into tee_pager_set_alias_area() and
tee_pager_generate_authenc_key(). The former function is called where
tee_pager_init() used to be called and

core: split tee_pager_init()

Splits tee_pager_init() into tee_pager_set_alias_area() and
tee_pager_generate_authenc_key(). The former function is called where
tee_pager_init() used to be called and the latter function is called
after the crypto API and RNG has been initialized.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: don't divide by sizeof(*mem) for ddr nsec memory

Since the two addresses are already of type struct core_mmu_phys_mem, do
not divide by sizeof(struct core_mmu_phys_mem). This broke dynamic sha

core: don't divide by sizeof(*mem) for ddr nsec memory

Since the two addresses are already of type struct core_mmu_phys_mem, do
not divide by sizeof(struct core_mmu_phys_mem). This broke dynamic shared
memory on Juno r0, since nelem would be zero for two slots.

Tested on Juno r0.

Fixes: 2f82082fada3 ("core: add ddr overall register")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Rouven Czerwinski <rouven@czerwinskis.de>

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plat-sunxi: Add plat-sunxi

Initial version support for Allwinner H2+ platform. Specific to Banana Pi
M2 zero board currently.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Je

plat-sunxi: Add plat-sunxi

Initial version support for Allwinner H2+ platform. Specific to Banana Pi
M2 zero board currently.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>

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core: add mdelay() function

checkpatch will check if udelay value is too large. Use udelay() to
implement mdelay() when we want to delay more than 10000 us.

Reviewed-by: Jens Wiklander <jens.wiklan

core: add mdelay() function

checkpatch will check if udelay value is too large. Use udelay() to
implement mdelay() when we want to delay more than 10000 us.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>

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Add new platform for the TI K3 class of SoCs

Add platform 'k3' for the TI K3 family. These are ARMv8 devices
and are quite different from our line of existing ARMv7 OMAP style
SoCs, hence the new pl

Add new platform for the TI K3 class of SoCs

Add platform 'k3' for the TI K3 family. These are ARMv8 devices
and are quite different from our line of existing ARMv7 OMAP style
SoCs, hence the new platform.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depend

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (defau

core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (default y)
which selects the C compiler flag -g3 and assembler flag -g.

DEBUG=1 is kept for compatibility.

Being able to compile without -g is useful to get much better performance
from ccache thanks to its 'unify' option [1].

Link: https://github.com/ccache/ccache/blob/v3.4.2/doc/MANUAL.adoc#configuration-settings
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000

plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START be100000 be100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START bfe00000 bfe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE be000000 be000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 0

plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START fe100000 fe100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START ffe00000 ffe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE fe000000 fe000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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