core: juno: workaround cortex-a57 errata 808870

Workaround errata 808870:
Unconditional VLDM instructions might cause an alignment fault even
though the address is aligned

Products Affected: Cortex

core: juno: workaround cortex-a57 errata 808870

Workaround errata 808870:
Unconditional VLDM instructions might cause an alignment fault even
though the address is aligned

Products Affected: Cortex-A57 MPCore.
Present in: r0p0

The workaround is to avoid generating the problematic instructions in
AArch32 TA.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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abort.c: arm32: assume VFP instr if undef

If an undefined instruction exception is raised from user mode assume it
is a VFP instruction unless VFP already is enabled.

This avoids reading user mode

abort.c: arm32: assume VFP instr if undef

If an undefined instruction exception is raised from user mode assume it
is a VFP instruction unless VFP already is enabled.

This avoids reading user mode memory while handling an abort which until
now has kept an undiscovered race where a page could become inaccessible
before the abort handler had the chance to read the instruction from the
page.

There is room for false positives. Those will be discovered the next
time the instruction is executed and still causes an undefined
instruction exception. Only this time VFP is already enabled so we know
it's not a VFP instruction. Enabling VFP in vain like this is harmless.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: prevent allocation when exception index tables are empty

This change prevent the core from allocating memory, mapping and
other resources to map exception index tables that are all empty.

Sig

core: prevent allocation when exception index tables are empty

This change prevent the core from allocating memory, mapping and
other resources to map exception index tables that are all empty.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: correct time conversion in delay support

The previous code may overflow in 32bit architectures. This change
fixes the issue by forcing 64bit computation during frequency
to counter conversion.

core: correct time conversion in delay support

The previous code may overflow in 32bit architectures. This change
fixes the issue by forcing 64bit computation during frequency
to counter conversion.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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thread: fix stack space to not be part of tee.bin

Commit 935364080364 ("thread: move stacks to separate sections") makes
stack space to be part of tee.bin which leads to approx. 130K increase
in siz

thread: fix stack space to not be part of tee.bin

Commit 935364080364 ("thread: move stacks to separate sections") makes
stack space to be part of tee.bin which leads to approx. 130K increase
in size of tee.bin for platform with 2 threads.
So this patch fixes the stack space to be in NOLOAD section only.

Fixes: 935364080364 ("thread: move stacks to separate sections")
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: fix saving vfp state

Prior to this patch TF-A in AArch32 didn't save the normal world VFP
data registers and thus always restored then as zeroes and causing
problems in normal world.

W

core: arm32: fix saving vfp state

Prior to this patch TF-A in AArch32 didn't save the normal world VFP
data registers and thus always restored then as zeroes and causing
problems in normal world.

With this patch if running with TF-A in AArch32 save the VFP state using
the same logic as in AArch64. Since TF-A saves and restores CPACR_EL1 we
cannot tell if normal world currently is using VFP or not so we have to
assume that it is and always save the VFP data registers if they are
about to be changed.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch32)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: user_ta: set freed EXIDX pointer to NULL

Clear reference of user TA exception index table once it
is freed, otherwise it is freed a second time. This
issue occurs when set_exidx() fails for so

core: user_ta: set freed EXIDX pointer to NULL

Clear reference of user TA exception index table once it
is freed, otherwise it is freed a second time. This
issue occurs when set_exidx() fails for some reasons as
an out of memory issue. This change prevents core from
panicking when it occurs.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: default guard reg_shm mobjs

Add a special guard for registered shared memory MOBJs to make sure that
it's not possible to release MOBJs which aren't created by an explicit
registration from no

core: default guard reg_shm mobjs

Add a special guard for registered shared memory MOBJs to make sure that
it's not possible to release MOBJs which aren't created by an explicit
registration from normal world.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mobj_reg_shm_free() using mobj_reg_shm_put()

Let reg_shm MOBJs be completely reference counted meaning that
mobj_free() on a reg_shm MOBJ only decrease the reference counter and
only free it i

core: mobj_reg_shm_free() using mobj_reg_shm_put()

Let reg_shm MOBJs be completely reference counted meaning that
mobj_free() on a reg_shm MOBJ only decrease the reference counter and
only free it if it reaches 0.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove mobj_reg_shm_{,un}map()

Removes mobj_reg_shm_map() and mobj_reg_shm_unmap(), they are replaced
by mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map().

Reviewed-by: Etienne Carriere <etie

core: remove mobj_reg_shm_{,un}map()

Removes mobj_reg_shm_map() and mobj_reg_shm_unmap(), they are replaced
by mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map().

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pta: use mobj_reg_shm_{inc,dec}_map()

Use mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map() instead of
mobj_reg_shm_map() and mobj_reg_shm_unmap().

Acked-by: Etienne Carriere <etienne.carrier

core: pta: use mobj_reg_shm_{inc,dec}_map()

Use mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map() instead of
mobj_reg_shm_map() and mobj_reg_shm_unmap().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add mobj_reg_shm_{inc,dec}_map()

mobj_reg_shm_inc_map() used when a reg_shm mobj needs to be mapped and
mobj_reg_shm_dec_map() is called when the mapping isn't needed any
longer.

Reviewed-by:

core: add mobj_reg_shm_{inc,dec}_map()

mobj_reg_shm_inc_map() used when a reg_shm mobj needs to be mapped and
mobj_reg_shm_dec_map() is called when the mapping isn't needed any
longer.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove reg_shm_{put,free}_by_cookie()

Removes the two functions mobj_reg_shm_put_by_cookie() and
mobj_reg_shm_free_by_cookie(). mobj_reg_shm_put() and mobj_free() should
be used instead.

Revi

core: remove reg_shm_{put,free}_by_cookie()

Removes the two functions mobj_reg_shm_put_by_cookie() and
mobj_reg_shm_free_by_cookie(). mobj_reg_shm_put() and mobj_free() should
be used instead.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: entry_std: free/put by mobj in call cleanup

Use the mobj pointer instead of a shm_ref when cleaning up parameters
in cleanup_shm_refs() at the end of a call.

Reviewed-by: Etienne Carriere <e

core: entry_std: free/put by mobj in call cleanup

Use the mobj pointer instead of a shm_ref when cleaning up parameters
in cleanup_shm_refs() at the end of a call.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add mobj_reg_shm_put()

Adds mobj_reg_shm_put() for reference counting without cookie.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander

core: add mobj_reg_shm_put()

Adds mobj_reg_shm_put() for reference counting without cookie.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: correct memory layout trace

Buffers that end at end of the available address range which
may happen on 32bit machine fail have an end address that of
computed as 0. This change uses a 64bit ad

core: correct memory layout trace

Buffers that end at end of the available address range which
may happen on 32bit machine fail have an end address that of
computed as 0. This change uses a 64bit address computation
to prevent the displayed end address being 0.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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abort.c: always save VFP state with thread context

Saving VFP state requires a thread context, if none is available print
abort info and panic().

Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@e

abort.c: always save VFP state with thread context

Saving VFP state requires a thread context, if none is available print
abort info and panic().

Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Fixes: cfa34ec63699 ("abort.c: manipulate with VFP state only if thread is active")
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch64 pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: trace out size of the pager physical page pool

Add a nice info trace about the size of the pager physical
page pool.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by:

core: trace out size of the pager physical page pool

Add a nice info trace about the size of the pager physical
page pool.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: reference count registered shared memory

* Adds a reference counter to registered shared memory to make sure that
it's not unregistered while in use.
* Updates entry_std to use the reference

core: reference count registered shared memory

* Adds a reference counter to registered shared memory to make sure that
it's not unregistered while in use.
* Updates entry_std to use the reference counting functions

Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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entry_std: use READ_ONCE() to read from shared memory

Use the READ_ONCE() macro everywhere shared memory is read to make sure
that unexpected values can not be used.

Reviewed-by: Volodymyr Babchuk

entry_std: use READ_ONCE() to read from shared memory

Use the READ_ONCE() macro everywhere shared memory is read to make sure
that unexpected values can not be used.

Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: Support psci feature query

Support PSCI call to query features list. So that non-secure world
knows what features are supported by ATF. The feature list is based
on current implement

core: arm: imx: Support psci feature query

Support PSCI call to query features list. So that non-secure world
knows what features are supported by ATF. The feature list is based
on current implemented iMX psci functions.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Peng Fan <peng.fan@nxp.com>

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Fix copying dirty values in copy_in_params()

If the OP-TEE driver from the rich OS specifies a message with a number
of params < TEE_NUM_PARAMS, copy_in_params() will copy in undefined
values from p

Fix copying dirty values in copy_in_params()

If the OP-TEE driver from the rich OS specifies a message with a number
of params < TEE_NUM_PARAMS, copy_in_params() will copy in undefined
values from pt[i] (where i >= the number of params). This is because the
pt array is an uninitialized local value, and per the C99 standard
6.7.8:

If an object that has automatic storage duration is not initialized
explicitly, its value is indeterminate.

This change fixes this issue by clearing out the unused parts of pt.

Signed-off-by: Christopher Tam <godtamit@google.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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entry_std: use READ_ONCE in strategic places

Code that deals with command buffers follows rule
"read once, validate, use". Problem is that compiler
does not know about this rule, so it can optimize

entry_std: use READ_ONCE in strategic places

Code that deals with command buffers follows rule
"read once, validate, use". Problem is that compiler
does not know about this rule, so it can optimize out
temporary variables and read data twice from the shared
buffer.

READ_ONCE() will ensure that compiler will not try to
optimize such reads.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rpi3: Modify addresses to work with upstream TF-A.

The upstream arm-trusted-firmware reserves 0x10100000-0x11000000 for
secure DRAM. Change the address according to the upstream TF-A.

To help

plat-rpi3: Modify addresses to work with upstream TF-A.

The upstream arm-trusted-firmware reserves 0x10100000-0x11000000 for
secure DRAM. Change the address according to the upstream TF-A.

To help troubleshoot discrepancies, this commit goes well with the TF-A at
commit aa49bde8a3e8 ("rpi3: Move NS-DRAM out of the protected region")

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>

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core: arm32: generate gicv3 register access code

Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Gener

core: arm32: generate gicv3 register access code

Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Generic Interrupt Controller Architecture Specification GIC
architecture version 3.0 and version 4.0.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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