core: imx: add support for i.MX 8MP EVK

Add support for mx8mp platforms

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens

core: imx: add support for i.MX 8MP EVK

Add support for mx8mp platforms

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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imx: pm: add support for reset2 function

Add support for SYSTEM_RESET2, which asserts WDOG-generated reset signal
WDOG_RESET_B_DEB (internal reset).

For additional details check WDOGx_WCR fields de

imx: pm: add support for reset2 function

Add support for SYSTEM_RESET2, which asserts WDOG-generated reset signal
WDOG_RESET_B_DEB (internal reset).

For additional details check WDOGx_WCR fields description in iMX
Applications Processor Reference Manual.

Acked-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: sm: upgrade to PSCI 1.1

Add support for new functions, introduced in PSCI v1.1 spec [1] (all
are optional):
* SYSTEM_RESET2 - extends existing SYSTEM_RESET. It provides

core: arm: sm: upgrade to PSCI 1.1

Add support for new functions, introduced in PSCI v1.1 spec [1] (all
are optional):
* SYSTEM_RESET2 - extends existing SYSTEM_RESET. It provides
architectural reset definitions and vendor-specific
resets.
* MEM_PROTECT - provides protection against cold reboot attacks,
by ensuring that memory is overwritten before it is
handed over to an operating system loader.
* MEM_PROTECT_CHECK_RANGE - used to check whether a memory range is
protected by MEM_PROTECT.

[1] https://developer.arm.com/documentation/den0022/latest/

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: sm: replace function ids with hex values

Replace PSCI function id defines with full hex values, so it's easier
to validate existing values/add new one from PSCI spec updates.

Reviewed-by

core: arm: sm: replace function ids with hex values

Replace PSCI function id defines with full hex values, so it's easier
to validate existing values/add new one from PSCI spec updates.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: fix thread_disable_prealloc_rpc_cache()

Fixes thread_disable_prealloc_rpc_cache() to also NULL rpc_mobj when
freeing the shared memory object. Failing to do so might cause it
rpc_mobj pointer

core: fix thread_disable_prealloc_rpc_cache()

Fixes thread_disable_prealloc_rpc_cache() to also NULL rpc_mobj when
freeing the shared memory object. Failing to do so might cause it
rpc_mobj pointer to be used after free.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arch/arm/include/*.h: use U() for unsigned constants

Updates with the U() macro as described in the recently updated
coding guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked

core/arch/arm/include/*.h: use U() for unsigned constants

Updates with the U() macro as described in the recently updated
coding guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arch/arm/include/*.h: se BIT() and SHIFT_U32() macros

Uses the more safe BIT() and SHIFT_U32() macros instead of direct
shifting of 1 or some other constant integer.

Acked-by: Ruchika Gupta <r

core/arch/arm/include/*.h: se BIT() and SHIFT_U32() macros

Uses the more safe BIT() and SHIFT_U32() macros instead of direct
shifting of 1 or some other constant integer.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu.[ch]: use U() for unsigned constants

Updates with the U() macro as described in the recently updated coding
guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: J

core: core_mmu.[ch]: use U() for unsigned constants

Updates with the U() macro as described in the recently updated coding
guidelines.

Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: enable CAAM DSA

Enable CAAM DSA algorithm for all LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: imx: enable CAAM DSA

Enable CAAM DSA algorithm for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: rename struct tee_pager_area to vm_paged_region

Renames struct tee_pager_area to struct vm_paged_region and moves it
next to the declaration of struct vm_region. Since areas are now called
pag

core: rename struct tee_pager_area to vm_paged_region

Renames struct tee_pager_area to struct vm_paged_region and moves it
next to the declaration of struct vm_region. Since areas are now called
paged regions or regions also rename functions, variables and struct
members accordingly.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-E

core: enable FF-A with SPM Core at S-EL2

This enables support for FF-A with SPM Core at S-EL2 in a secure
hypervisor while OP-TEE is running at S-EL1 as a SP.
This configuration is also know as "S-EL2 SPMC" in the FFA specification.

Compile with CFG_CORE_SEL2_SPMC=y

Note that this is an experimental feature, ABIs etc may have
incompatible changes.

This depends on using the FF-A v4 patchset in the Linux kernel.

Reviewed-by: Jelle Sels <jelle.sels@arm.com>
Co-developed-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: FF-A ABI updates

Updates structs and definitions to follow FF-A version 1.0.

Use the special hard coded UUID (486178e0-e7f8-11e3-bc5e-0002a5d5c51b)
for the SP OP-TEE is when compiled fo

core: spmc: FF-A ABI updates

Updates structs and definitions to follow FF-A version 1.0.

Use the special hard coded UUID (486178e0-e7f8-11e3-bc5e-0002a5d5c51b)
for the SP OP-TEE is when compiled for FF-A.

Updates the FF-A OP-TEE message ABI to make room for struct
optee_msg_arg to be used for RPC for OPTEE_FFA_YIELDING_CALL_WITH_ARG.

struct thread_ctx::rpc_arg for the current thread will always hold a
pointer to the struct optee_msg_arg to be used for RPC.

With this allocation of shared memory can be pushed up one layer and be
done via the struct optee_msg_arg so the
OPTEE_FFA_YIELDING_CALL_RETURN_ALLOC_*_SHM and
OPTEE_FFA_YIELDING_CALL_RETURN_FREE_*_SHM can be removed making the FF-A
ABI a bit less complicated.

Changes OPTEE_FFA_UNREGISTER_SHM to be a blocking call instead of a
yielding call.

Removes the unused OPTEE_FFA_YIELDING_CALL_REGISTER_SHM.

Updates the return values from yielding calls to use the TEE_Result
values instead of FF-A one to use the error code from the correct layer.

Defines OPTEE_MSG_FMEM_INVALID_GLOBAL_ID to 0xffffffffffffffffff which
is used as an invalid global id instead of 0.

This is an ABI breakage which must be done in sync with the FF-A v4
patchset in the Linux kernel.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add a4 and a5 to thread_alloc_and_run()

Adds two parameters a4 and a5 to thread_alloc_and_run(),
thread_std_smc_entry() and __thread_std_smc_entry().

Zeroes are passed where the new parameter

core: add a4 and a5 to thread_alloc_and_run()

Adds two parameters a4 and a5 to thread_alloc_and_run(),
thread_std_smc_entry() and __thread_std_smc_entry().

Zeroes are passed where the new parameters are not needed.

This prepares for the next update of the FF-A ABI for OP-TEE where among
other things one more register is used by
OPTEE_FFA_YIELDING_CALL_WITH_ARG.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: add read_cntvct()

Adds read_cntvct() to read Counter-timer Virtual Count register.

Note that arm32 already have this function.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-of

arm64: add read_cntvct()

Adds read_cntvct() to read Counter-timer Virtual Count register.

Note that arm32 already have this function.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add thread_smccc()

Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first

core: add thread_smccc()

Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first 8 registers is then saved in
the argument struct.

With the new flag CFG_CORE_SEL2_SPMC configures OP-TEE to work with a
SPMC at S-EL2 instead of the dispatcher at EL3. The SMC instruction
should not be used when working with a SPMC, OP-TEE should instead use
the HVC instruction in such a configuration.

Without a SPMC at S-EL2 OP-TEE works with the dispatcher at EL3 with no
changes.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must us

Rename to barrier_read_counter_timer()

Renames barrier_read_cntpct() to barrier_read_counter_timer() to use a
neutral name for the counter.

With SPMC at S-EL2 OP-TEE will be virtualized and must use CNTVCT
instead of CNTPCT while the old physical OP-TEE must continue to use
CNTPCT.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: let struct tee_pager_area span multiple translation tables

Extends struct tee_pager_area to be able to span multiple translation
tables avoiding the need to split ranges into multiple a

core: pager: let struct tee_pager_area span multiple translation tables

Extends struct tee_pager_area to be able to span multiple translation
tables avoiding the need to split ranges into multiple areas in case a
range crosses a translation table boundary.

Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: enable CAAM DH

Enabled CAAM DH algorithm for all LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

core: imx: enable CAAM DH

Enable CAAM DH algorithm for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

plat-stm32mp1: enable SCMI PTA interface

Enable SCMI PTA for REE to interface SCMI services in a threaded context.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wikla

plat-stm32mp1: enable SCMI PTA interface

Enable SCMI PTA for REE to interface SCMI services in a threaded context.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: use new register_ddr() macro

As register_dynamic_shm() is being retired - switch to the new macro.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk

plat: rcar: use new register_ddr() macro

As register_dynamic_shm() is being retired - switch to the new macro.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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plat: rcar m3: Add support for 8GB version

Add support for M3 SOC with 8GB of RAM. In this case memory is organized in
two bank of 4GB. Renesas calls this variant 2x4g, so in OP-TEE we will have
fla

plat: rcar m3: Add support for 8GB version

Add support for M3 SOC with 8GB of RAM. In this case memory is organized in
two bank of 4GB. Renesas calls this variant 2x4g, so in OP-TEE we will have
flavor salvator_m3_2x4g.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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plat-stm32mp1: fix plat_scmi_get_channel() against invalid IDs

Fix plat_scmi_get_channel() to safely return NULL when channel ID
argument is invalid.

Signed-off-by: Etienne Carriere <etienne.carrie

plat-stm32mp1: fix plat_scmi_get_channel() against invalid IDs

Fix plat_scmi_get_channel() to safely return NULL when channel ID
argument is invalid.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: clock gating: atomic RCC registers access

Use io_{set|clr}bits32_stm32shregs() instead of io_{set|clr}bits32() for
SoC clock registers that must be locked while updated.

Signed-off-b

plat-stm32mp1: clock gating: atomic RCC registers access

Use io_{set|clr}bits32_stm32shregs() instead of io_{set|clr}bits32() for
SoC clock registers that must be locked while updated.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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