plat-sam: matrix: remove wrong quirk for matrix id

Previous comment stated that the ID breaks at id 73 which is not the
case according to the datasheet. Remove this quirk which allow the last
periph

plat-sam: matrix: remove wrong quirk for matrix id

Previous comment stated that the ID breaks at id 73 which is not the
case according to the datasheet. Remove this quirk which allow the last
peripherals to be configured correctly. CHIPID peripheral can now be
correctly accessed by normal world when delegated.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: Don't call get_embedded_dt() without CFG_EMBED_DT

Several pieces of stm32mp1 code call get_embedded_dt(), then use the
resulting pointer without checks, or initiate a panic if it is N

plat-stm32mp1: Don't call get_embedded_dt() without CFG_EMBED_DT

Several pieces of stm32mp1 code call get_embedded_dt(), then use the
resulting pointer without checks, or initiate a panic if it is NULL.
Thus hitting this code results in a non-working binary. For example:

"PLATFORM=stm32mp1 CFG_DT=y"

The get_embedded_dt() uses were #ifdef'd out based on CFG_DT. However,
as shown, this is problematic, as the calls assumed a valid fdt must
be returned. A non-NULL fdt can be guaranteed with CFG_EMBED_DT, so
use this as the basis for the #ifdefs.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: register main heap first

Swap heap1 and heap2 malloc pools registration in init_runtime()
(case CFG_WITH_PAGER=y) since heap2 is the main heap part, heap1
being always < 4kB. This change ensur

core: register main heap first

Swap heap1 and heap2 malloc pools registration in init_runtime()
(case CFG_WITH_PAGER=y) since heap2 is the main heap part, heap1
being always < 4kB. This change ensures the first heap pool registered
into bget is large enough regarding bget initial pool constraint while
heap2 might to too small for that purpose.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt: add option to generate DTB overlay at boot

When using a memory persistent across reboots for external dtb overlay
(DRAM for instance) OP-TEE will reuse the existing dtb overlay if
CFG_EXTE

core: dt: add option to generate DTB overlay at boot

When using a memory persistent across reboots for external dtb overlay
(DRAM for instance) OP-TEE will reuse the existing dtb overlay if
CFG_EXTERNAL_DTB_OVERLAY is used. This will result in a big overlay
with duplicated nodes. In order to allow having a fresh DTB overlay
at boot, add CFG_GENERATE_DTB_OVERLAY to generate the DTB overlay at
OP-TEE boot time.
Both CFG_GENERATE_DTB_OVERLAY and CFG_EXTERNAL_DTB_OVERLAY will now
consider using the dtb address provided in r2 as well as CFG_DT_ADDR
to create the overlay if not existing.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt: remove 0x in reserved memory node unit name

According to the device tree specification, 0x should not be provided
in the node unit name.

Signed-off-by: Clément Léger <clement.leger@bootli

core: dt: remove 0x in reserved memory node unit name

According to the device tree specification, 0x should not be provided
in the node unit name.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: support level 0 as base level

All background work is done for this enablement.
Once CFG_LPAE_ADDR_SPACE_BITS >= 40 level 0 is auto enabled.
According to ARM spec using 4KB granularity wi

core: lpae: support level 0 as base level

All background work is done for this enablement.
Once CFG_LPAE_ADDR_SPACE_BITS >= 40 level 0 is auto enabled.
According to ARM spec using 4KB granularity with
address space >= 40 bit auto enables level 0 page table.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1, qemuv8)
Tested-by: Jerome Forissier <jerome@forissier.org> (vexpress-qemu_armv8a)

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core: lpae: support user mapping when base level is 0

User mapping (i.e. TAs) is expected to be at level 2,
so an level 1 entry points to this mapping.
If base level is 1, as it was supported, nothi

core: lpae: support user mapping when base level is 0

User mapping (i.e. TAs) is expected to be at level 2,
so an level 1 entry points to this mapping.
If base level is 1, as it was supported, nothing changes.
If base level is 0 then an extra page is created at level 1,
so user mapping can be pointed from level 1 entry, as it's
supported by user mappings.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: add internal core_mmu_entry_copy()

core_mmu_entry_copy() takes a table entry that point to other
table, allocate a new table, copy the content of the original table,
and eventually make

core: lpae: add internal core_mmu_entry_copy()

core_mmu_entry_copy() takes a table entry that point to other
table, allocate a new table, copy the content of the original table,
and eventually make the higher level table point to the new table.
This function is useful to copy mapping tables from core to core.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: add internal core_mmu_xlat_table_entry_pa2va()

core_mmu_xlat_table_entry_pa2va() allows to get the virtual address
of a table pointed by some other table entry.
Current it has a single u

core: lpae: add internal core_mmu_xlat_table_entry_pa2va()

core_mmu_xlat_table_entry_pa2va() allows to get the virtual address
of a table pointed by some other table entry.
Current it has a single use, but it will have few more usages later.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: lpae: search TAs VA base in the regions [1GB, 4GB[

In order to support 32-bit TAs we will have to find
a TAs VA base in the region of [1GB, 4GB[.
The 4GB limit wasn't enforced before this patc

core: lpae: search TAs VA base in the regions [1GB, 4GB[

In order to support 32-bit TAs we will have to find
a TAs VA base in the region of [1GB, 4GB[.
The 4GB limit wasn't enforced before this patch.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: extract 48 bits from table entry

Page table entry descriptor holds 48 bits of PA,
while only 40 were extracted.
This change is crucial to support more than 40 bits of addressing.

Signed

core: lpae: extract 48 bits from table entry

Page table entry descriptor holds 48 bits of PA,
while only 40 were extracted.
This change is crucial to support more than 40 bits of addressing.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: mmu: replace "1 << x" with "BIT64(x)"

"1" instead of "1ULL" caused issues with calculations
when address width is higher than 32 bits.
Uses BIT64() instead of explicit "1ULL".

Signed-off-by:

core: mmu: replace "1 << x" with "BIT64(x)"

"1" instead of "1ULL" caused issues with calculations
when address width is higher than 32 bits.
Uses BIT64() instead of explicit "1ULL".

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: use "base table" naming instead of "l1 table"

This is a preparation for supporting base table
which is not level 1 (i.e. support level 0).
Tries not to change anything functional, but
ra

core: lpae: use "base table" naming instead of "l1 table"

This is a preparation for supporting base table
which is not level 1 (i.e. support level 0).
Tries not to change anything functional, but
rather just a renaming.
"base table" terminology is referenced from TF-A
Renamed CORE_MMU_L1_TBL_OFFSET -> CORE_MMU_BASE_TABLE_OFFSET
Added CORE_MMU_BASE_TABLE_LEVEL instead of hard-coded "1"
Added CORE_MMU_BASE_TABLE_SHIFT instead of hard-coded "30"
Few new defines were copied from TF-A xlat_tables_def.h,
like the existing XLAT related defines.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: replace "3" with XLAT_TABLE_LEVEL_MAX

Just a cosmetic change for a better code readability.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@lina

core: lpae: replace "3" with XLAT_TABLE_LEVEL_MAX

Just a cosmetic change for a better code readability.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: lpae: fix 'idx' boundary check in core_mmu_entry_to_finer_grained()

Table entry index, 'idx', was checked for [0, tbl_info->num_entries],
while it should be [0, tbl_info->num_entries[.

Signed

core: lpae: fix 'idx' boundary check in core_mmu_entry_to_finer_grained()

Table entry index, 'idx', was checked for [0, tbl_info->num_entries],
while it should be [0, tbl_info->num_entries[.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Fix r7 clobbering in reset_primary

During reset_primary, r7 is used to keep the content of r2 register
given at OP-TEE start. However, r7 is clobbered during boot. This lead
to r2 being incorr

core: Fix r7 clobbering in reset_primary

During reset_primary, r7 is used to keep the content of r2 register
given at OP-TEE start. However, r7 is clobbered during boot. This lead
to r2 being incorrectly restored when returning to normal world. Use
r9 instead of r7 where needed to avoid clobbering it.

Fixes: 59ac3801b756 ("core: split boot_init_primary")
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm64: remove duplicate definition of THREAD_CTX_SIZE

Following commit 1b302ac09816 ("core: enable FF-A with SPM Core at
S-EL1"), the THREAD_CTX_SIZE macro is now defined twice on arm64
(in $(

core: arm64: remove duplicate definition of THREAD_CTX_SIZE

Following commit 1b302ac09816 ("core: enable FF-A with SPM Core at
S-EL1"), the THREAD_CTX_SIZE macro is now defined twice on arm64
(in $(out-dir)/core/include/generated/asm-defines.h).

Kill the definition in the #ifdef ARM64 block and keep the common
one.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because

core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because physical
address can be mapped in the same time in different virtual
regions with different length. So the first found region
which contains the requested physical address possibly
doesn`t have enough mapped data. This is fixed by adding
the length parameter to phys_to_virt() function. Length
parameter can be set to 1 if caller knows that requested
(pa + len) doesn`t cross mapping granule boundary.

core_mmu_get_va() and io_pa_or_va() functions now are
take length parameter too as they based on phys_to_virt()
in case of MMU enabled.

Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)

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core: arm: implement cpu_idle()

Implement cpu_idle() on arm and arm64, based on wfi(). With this patch,
a panicked CPU no longer burns cycles needlessly.

Signed-off-by: Jerome Forissier <jerome@for

core: arm: implement cpu_idle()

Implement cpu_idle() on arm and arm64, based on wfi(). With this patch,
a panicked CPU no longer burns cycles needlessly.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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arm64: add wfi()

arm32.h has a wfi() function but not arm64.h. Add it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Et

arm64: add wfi()

arm32.h has a wfi() function but not arm64.h. Add it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: rename TA_VASPACE to TS_VASPACE

The TA_VASPACE memory will be used by both TAs and SPs.
Rename it to TS_VASPACE so it is clearer that it can be used by both.

Signed-off-by: Jelle Sels <jelle.

core: rename TA_VASPACE to TS_VASPACE

The TA_VASPACE memory will be used by both TAs and SPs.
Rename it to TS_VASPACE so it is clearer that it can be used by both.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-totalcompute: Introduce TC1 platform

The different platform parameters, such as GIC, UART, etc
are similar between TC0 and TC1. tc0_spmc_pm.c is also renamed to
tc_spmc_pm.c as its common to bo

plat-totalcompute: Introduce TC1 platform

The different platform parameters, such as GIC, UART, etc
are similar between TC0 and TC1. tc0_spmc_pm.c is also renamed to
tc_spmc_pm.c as its common to both platforms.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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mm: fix mobj split by adding core_mmu_find_mapping_exclusive() helper

Fixes: ff01e2452169 ("mm: split mobj_tee_ram onto rw/rx parts")

This fixes mobj splitting onto RX/RW parts. Now split can be do

mm: fix mobj split by adding core_mmu_find_mapping_exclusive() helper

Fixes: ff01e2452169 ("mm: split mobj_tee_ram onto rw/rx parts")

This fixes mobj splitting onto RX/RW parts. Now split can be done
incorrectly if RX and RW regions doesn`t mapped contiguosly. Added helper
core_mmu_find_mapping_exclusive() allows to find unique mapping for
specified type and length independently of their order, so then RX/RW
regions for mobjects should be determined correctly.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>

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core: add new init and nexus memory types

Adds the new memory types MEM_AREA_INIT_RAM_RO, MEM_AREA_INIT_RAM_RX and
MEM_AREA_NEX_RAM_RO to make sure that the memory types
MEM_AREA_TEE_RAM_RX, MEM_ARE

core: add new init and nexus memory types

Adds the new memory types MEM_AREA_INIT_RAM_RO, MEM_AREA_INIT_RAM_RX and
MEM_AREA_NEX_RAM_RO to make sure that the memory types
MEM_AREA_TEE_RAM_RX, MEM_AREA_TEE_RAM_RO and MEM_AREA_TEE_RAM_RW are
used only once. This is needed when to uniquely identify those memory
areas in mobj_init() and mobj_phys_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Anton Rybakov <a.rybakov@omp.ru>

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plat-marvell: Add HUK support for OcteonTX2 Platforms

Added support for fetching Hardware Unique Key(HUK)
from the OcteonTX2 platform.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Reviewed

plat-marvell: Add HUK support for OcteonTX2 Platforms

Added support for fetching Hardware Unique Key(HUK)
from the OcteonTX2 platform.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Reviewed-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Reviewed-by: Bharat Bhushan <bbhushan2@marvell.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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