| d2c399da | 19-Jul-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: enable PSCI shutdown support
Enable PSCI shutdown support using atmel shutdown controller driver.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.
plat-sam: enable PSCI shutdown support
Enable PSCI shutdown support using atmel shutdown controller driver.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
show more ...
|
| eee289a2 | 19-Jul-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: enable PSCI reset support
Enable PSCI reset support using atmel reset controller driver.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@
plat-sam: enable PSCI reset support
Enable PSCI reset support using atmel reset controller driver.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
show more ...
|
| c86153f3 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: enable PSCI_ARM32, ATMEL_SHDWC and ATMEL_RSTC
Enable config PSCI_ARM32, ATMEL_SHDWC and ATMEL_RSTC to implement basic PSCI support. Force enable PSCI_ARM32 but allow other options to be mo
plat-sam: enable PSCI_ARM32, ATMEL_SHDWC and ATMEL_RSTC
Enable config PSCI_ARM32, ATMEL_SHDWC and ATMEL_RSTC to implement basic PSCI support. Force enable PSCI_ARM32 but allow other options to be modified if shutdown and reset is not needed.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
show more ...
|
| 7736c4e4 | 28-Apr-2021 |
Jelle Sels <jelle.sels@arm.com> |
core: FF-A: Add FFA_MEM_RECLAIM support
FFA_MEM_RECLAIM is used by a SP to retract given access to a memory region. Afterwards the SP has full exclusive ownership of the memory region again. After c
core: FF-A: Add FFA_MEM_RECLAIM support
FFA_MEM_RECLAIM is used by a SP to retract given access to a memory region. Afterwards the SP has full exclusive ownership of the memory region again. After calling FFA_MEM_RECLAIM all bookkeepings of the share are removed from the SPMC.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| c1aadcc7 | 03-Sep-2021 |
Jelle Sels <jelle.sels@arm.com> |
core: FF-A: Add FFA_MEM_RELINQUISH
FFA_MEM_RELINQUISH is used by a SP to release a memory share that was claimed by calling FFA_MEM_RETRIEVE_REQ_64 before. The memory region will be unmapped from th
core: FF-A: Add FFA_MEM_RELINQUISH
FFA_MEM_RELINQUISH is used by a SP to release a memory share that was claimed by calling FFA_MEM_RETRIEVE_REQ_64 before. The memory region will be unmapped from the SPs memory once FFA_MEM_RELINQUISH has been called the same amount of times as FFA_MEM_RETRIEVE_REQ_64.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| de66193d | 06-Sep-2021 |
Jelle Sels <jelle.sels@arm.com> |
core: FF-A: ADD FFA_MEM_RETRIEVE for SPs
FFA_MEM_RETRIEVE is used by a SP to retrieve a FF-A memory share with a handle. Once the FFA_MEM_RETRIEVE message is handled correctly the corresponding memo
core: FF-A: ADD FFA_MEM_RETRIEVE for SPs
FFA_MEM_RETRIEVE is used by a SP to retrieve a FF-A memory share with a handle. Once the FFA_MEM_RETRIEVE message is handled correctly the corresponding memory region is mapped into the SPs memory
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 6a1b230c | 13-Sep-2021 |
Jelle Sels <jelle.sels@arm.com> |
core: FFA_SHARE: Process Normal World share
Process a FFA_SHARE command coming from the Normal World. When receiving a FFA_SHARE message from the Normal World, we check the first receiver endpoint i
core: FFA_SHARE: Process Normal World share
Process a FFA_SHARE command coming from the Normal World. When receiving a FFA_SHARE message from the Normal World, we check the first receiver endpoint id. If the endpoint id is that off the OP_TEE endpoint, we let the thread_spmc handler handle the share. If it is not, we process it inside the spmc_sp_handler. The mobj_ffa_() functions are used to create a new mobj for each new share and to keep track of them.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 72ede99e | 13-Sep-2021 |
Jelle Sels <jelle.sels@arm.com> |
core: FFA_SHARE: Process secure share
Process a FFA_SHARE command coming from a SP. When receiving a FFA_SHARE message from a SP, we don't create any new mobj's. Instead we retrieve the mobj's from
core: FFA_SHARE: Process secure share
Process a FFA_SHARE command coming from a SP. When receiving a FFA_SHARE message from a SP, we don't create any new mobj's. Instead we retrieve the mobj's from the SP list off already mapped mobj's via vm_get_mobj(). For each FFA_SHARE we check that the memory regions are mapped and not shared with any other endpoints.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| cdd7a3f4 | 13-Sep-2021 |
Jelle Sels <jelle.sels@arm.com> |
core: FFA_SHARE: Process receiver data
Process the receiver specific data of a FFA_SHARE command. Store the receiver and link it to the endpoints (SPs).
Signed-off-by: Jelle Sels <jelle.sels@arm.co
core: FFA_SHARE: Process receiver data
Process the receiver specific data of a FFA_SHARE command. Store the receiver and link it to the endpoints (SPs).
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 5c1143a8 | 13-Sep-2021 |
Jelle Sels <jelle.sels@arm.com> |
core: FFA_SHARE: Process FFA_MEM_SHARE message
Process a FF-A FFA_MEM_SHARE message coming from a SP or being sent from the Normal world with one or more SPs receivers. FFA_MEM_SHARE is used to shar
core: FFA_SHARE: Process FFA_MEM_SHARE message
Process a FF-A FFA_MEM_SHARE message coming from a SP or being sent from the Normal world with one or more SPs receivers. FFA_MEM_SHARE is used to share a memory region from an endpoint (SP or normal world) with one or more endpoints in secure world(SPs).
A simplified version of the share memory transaction descriptor looks like the following:
|-------------------| |ffa_mem_transaction| Contains general data for the whole share |-------------------| |mem_access_array[0]| Contains information specific for each receiver SP |-------------------| |mem_access_array[1]| |-------------------| |mem_access_array[n]| |-------------------| |ffa_mem_region | Contains the memory which is shared |-------------------|
Add sp_mem as a new memory object. Sp_mem is used to store all information needed for a FF-A share. For each new FF-A share a sp_mem object is created. Each share is stored inside the mem_shares list inside sp_mem.c
The ffa_mem_transaction data is stored inside the sp_mem object. The receivers list inside sp_mem is used to store all the ffa_mem_region related data. The regions list is used to store all data related to the mem_access_array. A mobj reference is will be used to map the region into the SPs endpoint.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| c6726b47 | 14-Oct-2021 |
Jelle <jelle.sels@arm.com> |
FF-A: Add macro for FF-A memory cookie bit
When creating a new cookie of the mobj_ffa a BIT64(44) was used inline. Create a macro for it.
Signed-off-by: Jelle <jelle.sels@arm.com> Reviewed-by: Jens
FF-A: Add macro for FF-A memory cookie bit
When creating a new cookie of the mobj_ffa a BIT64(44) was used inline. Create a macro for it.
Signed-off-by: Jelle <jelle.sels@arm.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 3b012d52 | 02-Jul-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: set QSPI memories as non secure
When left unconfigured, the QSPI memories are assigned to the secure world. However, the controller is assigned to normal world and Linux expects to use QPS
plat-sam: set QSPI memories as non secure
When left unconfigured, the QSPI memories are assigned to the secure world. However, the controller is assigned to normal world and Linux expects to use QPSI memories with it which will fail because they are not accessible. Configure them to be accessible by the normal world in order to let Linux handle the QSPI controller properly.
Acked-by: Jerome Forissier <jerome@forissier.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
show more ...
|
| c44e5389 | 10-Jun-2021 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat-imx: add Advantech RSB-3720 board support
Support for Advantech RSB-3720 board (imx8mp). (PLATFORM=imx-mx8mp_rsb3720_6g)
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Acked-by: J
plat-imx: add Advantech RSB-3720 board support
Support for Advantech RSB-3720 board (imx8mp). (PLATFORM=imx-mx8mp_rsb3720_6g)
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Acked-by: Jerome Forissier <jerome@forissier.org> Acked-by: Clement Faure <clement.faure@nxp.com>
show more ...
|
| 7b06f6ca | 03-May-2021 |
Jens Wiklander <jens.wiklander@linaro.org> |
qemu: enable testing of notifications using the console
When asynchronous notifications are enabled the console driver in qemu is configured as a top half and bottom half driver allowing basic testi
qemu: enable testing of notifications using the console
When asynchronous notifications are enabled the console driver in qemu is configured as a top half and bottom half driver allowing basic testing of the notification framework.
Reviewed-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| c2d44948 | 20-Apr-2021 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add asynchronous notifications
Adds support for asynchronous notifications from secure world to normal world. This allows a design with a top half and bottom half type of driver where the top
core: add asynchronous notifications
Adds support for asynchronous notifications from secure world to normal world. This allows a design with a top half and bottom half type of driver where the top half runs in secure interrupt context and a notifications tells normal world to schedule a yielding call to do the bottom half processing.
The protocol is defined in optee_msg.h optee_rpc_cmd.h and optee_smc.h.
A notification consists of a 32-bit value which normal world can retrieve using a fastcall into secure world. OP-TEE is currently only supporting the value 0-63 where 0 has a special meaning. When 0 is sent it means that normal world is supposed to make a yielding call OPTEE_MSG_CMD_DO_BOTTOM_HALF.
The notification framework in OP-TEE defines an interface where drivers can register a callback which is called on each yielding bottom half call.
Notification capability is negotiated with the normal world while it initializes its driver. If both sides supports these notifications then they are enabled.
CFG_CORE_ASYNC_NOTIF_GIC_INTID is added to define the hardware interrupt used to notify normal world. This is added to the DTB in case OP-TEE can is configured with CFG_DT=y. Other cases requires the normal world DTB to be kept in sync with this.
Reviewed-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| e812b2d0 | 10-May-2021 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: optee_smc.h: clarify calls with struct optee_msg_arg
Clarifies the responsibilities of the caller when calling with struct optee_msg_arg as argument.
Reviewed-by: Jerome Forissier <jerome@for
core: optee_smc.h: clarify calls with struct optee_msg_arg
Clarifies the responsibilities of the caller when calling with struct optee_msg_arg as argument.
Reviewed-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 48685b6c | 16-Dec-2021 |
Jerome Forissier <jerome@forissier.org> |
arm64: bti: fail link phase if some objects do not support BTI
Adds the proper linker options (-z force-bti --fatal-warnings) to fail the link if some object files lack the BTI feature bit when BTI
arm64: bti: fail link phase if some objects do not support BTI
Adds the proper linker options (-z force-bti --fatal-warnings) to fail the link if some object files lack the BTI feature bit when BTI is requested (CFG_CORE_BTI=Y, CFG_TA_BTI=y). The options are added for tee.elf, ldelf.elf, in-tree TAs, in-tree user space shared libraries (CFG_ULIBS_SHARED=y) as well as for external TAs and shared libraries built with the dev kit.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Ruchika Gupta <ruchika.gupta@linaro.org>
show more ...
|
| 181f8492 | 06-Dec-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
Generate ELF Note for BTI in all arm64 asm files
Add program property note section in the assembly files to ensure that when linking them, program property note section is generated in the final ELF
Generate ELF Note for BTI in all arm64 asm files
Add program property note section in the assembly files to ensure that when linking them, program property note section is generated in the final ELF.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| e768d3d5 | 02-Nov-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
arm64: bti: Support building user mode libraries with BTI
When running with BTI enabled we need to ask the compiler to enable generation of BTI landing pads. With this option enabled, all C source f
arm64: bti: Support building user mode libraries with BTI
When running with BTI enabled we need to ask the compiler to enable generation of BTI landing pads. With this option enabled, all C source files compiled for user mode libraries or Trusted Application will be compiled with BTI.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| a91fbe0f | 02-Nov-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
core: ldelf: Enable GP bit when creating mapping for ldelf
Since ldelf loader is compiled with BTI if CFG_CORE_BTI is enabled, mark the GP bit when creating mapping for ldelf in user space.
Signed-
core: ldelf: Enable GP bit when creating mapping for ldelf
Since ldelf loader is compiled with BTI if CFG_CORE_BTI is enabled, mark the GP bit when creating mapping for ldelf in user space.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| d707c30c | 02-Nov-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
core: mm: Set GP bit to enable BTI for TEE core
For all the descriptor entries marked with TEE_MATTR_PX, enable GP bit if BTI is enabled.
TEE_MATTR_GUARDED attribute is also added here. This will b
core: mm: Set GP bit to enable BTI for TEE core
For all the descriptor entries marked with TEE_MATTR_PX, enable GP bit if BTI is enabled.
TEE_MATTR_GUARDED attribute is also added here. This will be used when creating mapping for user space.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Acked-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 13a1e5cb | 02-Dec-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
arm64: Add support for reading register ID_AA64PFR1_EL1
Register ID_AA64PFR1_EL1 provides information about implemented PE features in AArch64 state. Read it to determine if BTI mechanism is support
arm64: Add support for reading register ID_AA64PFR1_EL1
Register ID_AA64PFR1_EL1 provides information about implemented PE features in AArch64 state. Read it to determine if BTI mechanism is supported or not.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 7ad2713d | 19-Nov-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
Add BTI launch pads in aarch64 assembly files
Compiler adds BTI launchpads only in C source files. For assembly files, BTI launchpad is also required at locations where "br" is used and at the start
Add BTI launch pads in aarch64 assembly files
Compiler adds BTI launchpads only in C source files. For assembly files, BTI launchpad is also required at locations where "br" is used and at the start of the functions. This needs to be added manually.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 03bada66 | 19-Nov-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
libutils: asm.S : Introduce parameter _bti in FUNC's
There are few places where the original macros FUNC and LOCAL_FUNC are used to define vector tables or exception vector tables. To take care of s
libutils: asm.S : Introduce parameter _bti in FUNC's
There are few places where the original macros FUNC and LOCAL_FUNC are used to define vector tables or exception vector tables. To take care of such assembly code where BTI is not needed, introduce new parameter _bti. If the _bti passed to the function is not default, don't add BTI launchpad to the function.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 3991ef11 | 02-Nov-2021 |
Ruchika Gupta <ruchika.gupta@linaro.org> |
arm64: bti: Support building TEE core C files with BTI
When running with BTI enabled we need to ask the compiler to enable generation of BTI landing pads. With this option enabled, all C source file
arm64: bti: Support building TEE core C files with BTI
When running with BTI enabled we need to ask the compiler to enable generation of BTI landing pads. With this option enabled, all C source files compiled for TEE Core including the kernel versions of libraries such as libutils.a will be compiled with BTI. This also includes ldelf loader C files.
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> Reviewed-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|