plat-stm32mp1: support STM32MP13 gpio bank resources

STM32MP13 platform does not support the same amount of GPIO bank.

Always define the util functions. Support STM32MP13 and STM32MP15.

Signed-off

plat-stm32mp1: support STM32MP13 gpio bank resources

STM32MP13 platform does not support the same amount of GPIO bank.

Always define the util functions. Support STM32MP13 and STM32MP15.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: scmi_server update for STM32MP13

Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.

This change also remove the '0' index to the SCMI domains

plat-stm32mp1: scmi_server update for STM32MP13

Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.

This change also remove the '0' index to the SCMI domains in order to
align with Linux kernel.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add initial support of STM32MP135F-DK board

Add support of STM32MP135F discovery board (part number:
STM32MP135F-DK) that integrates a STM32MP135F SoC with 512 MB of DDR3.

The board pro

dts: stm32: add initial support of STM32MP135F-DK board

Add support of STM32MP135F discovery board (part number:
STM32MP135F-DK) that integrates a STM32MP135F SoC with 512 MB of DDR3.

The board provides SDcard and USB mass storage as persistent storage
device interfaces.

Co-developed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-st

dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-storage: 3*SDMCC, 1*QSPI, FMC
-com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
-audio: 2*SAI
-network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC

Co-developed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Disable SA2UL RNG driver on unsupported flavors

Only enable the SA2UL TRNG on platform flavors that are currently
supported. This can be relaxed for platforms as support is verifie

plat-k3: drivers: Disable SA2UL RNG driver on unsupported flavors

Only enable the SA2UL TRNG on platform flavors that are currently
supported. This can be relaxed for platforms as support is verified.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: kernel: fix rpc shm free when prealloc is disable

Fixes commit [1] that changed implementation of the standard invocation
SMC command to introduce invocation with RPC shared memory refere

core: arm: kernel: fix rpc shm free when prealloc is disable

Fixes commit [1] that changed implementation of the standard invocation
SMC command to introduce invocation with RPC shared memory reference.
A wrong logic was implemented to free RPC buffer on standard invocation
completion. This change fixes that by freeing the cached shared memory
when pre-allocation is disable by config switch or runtime service.

Fixes: feb290a51087 ("core: add OPTEE_SMC_CALL_WITH_RPC_ARG")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: plat-ls: correct expression CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE

There was no parenthesis around CFG_TEE_CORE_NB_CORE
when assigning it to CFG_NUM_THREADS, so corrected it.

Signed-off-by:

core: plat-ls: correct expression CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE

There was no parenthesis around CFG_TEE_CORE_NB_CORE
when assigning it to CFG_NUM_THREADS, so corrected it.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: plat-ls: remove OP-TEE support for LS1012A-FRWY platform

LS1012A-FRWY does not support OP-TEE anymore, removing its
support.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: J

core: plat-ls: remove OP-TEE support for LS1012A-FRWY platform

LS1012A-FRWY does not support OP-TEE anymore, removing its
support.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-ls: set CFG_NUM_THREADS ?= 2 for LS1012ARDB

xtest regression_1009.3 fails on LS1012ARDB because the test needs
at least two threads but the default configuration for the platform
enables

core: plat-ls: set CFG_NUM_THREADS ?= 2 for LS1012ARDB

xtest regression_1009.3 fails on LS1012ARDB because the test needs
at least two threads but the default configuration for the platform
enables only one. Set CFG_NUM_THREADS ?= 2 to fix the issue.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: fix tzsram_end in init_runtime()

With pager enabled tzsram_end in init_runtime() is supposed to be a
virtual address. However TZSRAM_BASE is a physical address so this only
works as lon

core: pager: fix tzsram_end in init_runtime()

With pager enabled tzsram_end in init_runtime() is supposed to be a
virtual address. However TZSRAM_BASE is a physical address so this only
works as long as virtual and physical addresses can be used
interchangeably. With ASLR enabled this is not the case so fix this to
compensate for the offset between physical and virtual addresses.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: nsec-service: handle SMC to set USB suspend

Handle the SMC that allows Linux to set USB suspend mode using the SFR.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne

plat-sam: nsec-service: handle SMC to set USB suspend

Handle the SMC that allows Linux to set USB suspend mode using the SFR.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: sfr: add function to set usb suspend

This function allows to set the usb suspend mode using the SFR
peripheral. This will be used to execute a SMC that is going to be
issued by Linux sama5

plat-sam: sfr: add function to set usb suspend

This function allows to set the usb suspend mode using the SFR
peripheral. This will be used to execute a SMC that is going to be
issued by Linux sama5 USB driver.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: sfr: set as secure if specified by the device-tree

The SFR can be set as secure using the matrix peripheral. If set as
secure-status = "okay" and status = "disabled" in the device-tree, th

plat-sam: sfr: set as secure if specified by the device-tree

The SFR can be set as secure using the matrix peripheral. If set as
secure-status = "okay" and status = "disabled" in the device-tree, then
configure the SFR as secure.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: sfr: simplify code for sam_sfr_base()

Simplify the code logic to have less imbricated if().

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carrie

plat-sam: sfr: simplify code for sam_sfr_base()

Simplify the code logic to have less imbricated if().

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: split SFR code out of main.c file

Move SFR specific code to sam_sfr.c file.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
S

plat-sam: split SFR code out of main.c file

Move SFR specific code to sam_sfr.c file.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-stm32mp1: support rng pta with secure RNG source

Changes platform stm32mp1 configuration to default enable RNG PTA
support when CFG_WITH_SOFTWARE_PRNG is disable. This configuration
mandates st

plat-stm32mp1: support rng pta with secure RNG source

Changes platform stm32mp1 configuration to default enable RNG PTA
support when CFG_WITH_SOFTWARE_PRNG is disable. This configuration
mandates stm32mp1 RNG device and its resources to be assigned to the
secure world to be accessible at runtime.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: implement plat_rng_init()

Moves plat_rng_init() definition from platform source file rng_seed.c
to core driver source stm32_rng.c. There is no platform magic needed
in this funct

drivers: stm32_rng: implement plat_rng_init()

Moves plat_rng_init() definition from platform source file rng_seed.c
to core driver source stm32_rng.c. There is no platform magic needed
in this function. As a result, seed_rng.c source file is removed.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: seed PRNG with initialized rng device

Simplifies platform rng_seed.c implementation. Since a previous change
initializes stm32_rng driver before plat_rng_init() is called, it is now
p

plat-stm32mp1: seed PRNG with initialized rng device

Simplifies platform rng_seed.c implementation. Since a previous change
initializes stm32_rng driver before plat_rng_init() is called, it is now
possible to use stm32_rng_read() to get PRNG seed. The sequence is
simplified as stm32_rng_read() takes care of device resource dependencies.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-zynqmp: Added __nex_bss symbol for virtualization support

Without the __nex_bss symbol added to gic_data and console_data
the zynqmp platform results in a deadlock when attempting
to write to t

plat-zynqmp: Added __nex_bss symbol for virtualization support

Without the __nex_bss symbol added to gic_data and console_data
the zynqmp platform results in a deadlock when attempting
to write to the serial device on the platform. This fix resolves
the deadlock issue. More details can be found in the referred link.

Link: https://github.com/OP-TEE/optee_os/issues/5384
Signed-off-by: Michael Doran <michael.doran@dornerworks.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: Enable handling 64-bit direct messages

Enable using the 64-bit version of the FF-A direct request and response
calls.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Et

core: ffa: Enable handling 64-bit direct messages

Enable using the 64-bit version of the FF-A direct request and response
calls.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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plat-synquacer: rename rng_pta.h to synquacer_rng_pta.h

Renames plat-synquacer rng_pta.h to synquacer_rng_pta.h to prevent
confusion with generic RNG PTA header file pta_rng.h.

Acked-by: Jerome For

plat-synquacer: rename rng_pta.h to synquacer_rng_pta.h

Renames plat-synquacer rng_pta.h to synquacer_rng_pta.h to prevent
confusion with generic RNG PTA header file pta_rng.h.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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pta: rng: rename rng_pta_client.h to pta_rng.h

Renames RNG PTA exported header file from rng_pta_client.h to pta_rng.h
as the later follows PTAs header file name convention in optee_os
that is pta_x

pta: rng: rename rng_pta_client.h to pta_rng.h

Renames RNG PTA exported header file from rng_pta_client.h to pta_rng.h
as the later follows PTAs header file name convention in optee_os
that is pta_xxx.h.

Preserve rng_pta_client.h for backward compatibility. That header file
only includes pta_rng.h.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: imx: dcp: disable the use of UNIQUE KEY after HUK generation

Disable the use of DCP unique key (0xfe in the DCP key selection) after
the HUK generation.
The DCP unique key is used to genera

drivers: imx: dcp: disable the use of UNIQUE KEY after HUK generation

Disable the use of DCP unique key (0xfe in the DCP key selection) after
the HUK generation.
The DCP unique key is used to generate the HUK at boot time. Disabling
the use of the unique key prevents the non-secure world from
re-generating the HUK.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Ricardo Salveti <ricardo@foundries.io> (imx-mx6ullevk)

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plat-stm32mp1: restore reserved shared memory

Restores OP-TEE reserved shared memory (the last MBytes of DRAM located
on top of the secure DDR) in STM32MP15 default configuration. This
default confi

plat-stm32mp1: restore reserved shared memory

Restores OP-TEE reserved shared memory (the last MBytes of DRAM located
on top of the secure DDR) in STM32MP15 default configuration. This
default configuration is needed to support mainline TF-A in conjunction
with mainline Linux kernel.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-hikey: Add embedded DTB to define SDP

For Hikey, the Secure Data Path memory region definition is
done in an embedded dtb as defined in
Documentation/devicetree/bindings/reserved-memory/linaro,

plat-hikey: Add embedded DTB to define SDP

For Hikey, the Secure Data Path memory region definition is
done in an embedded dtb as defined in
Documentation/devicetree/bindings/reserved-memory/linaro,secure-heap.yaml

Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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