plat-stm32mp1: remove deprecated shared_resource driver

Remove stm32mp1 platform shared_resources.c driver that is no more used.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked

plat-stm32mp1: remove deprecated shared_resource driver

Remove stm32mp1 platform shared_resources.c driver that is no more used.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rng: implement plat_rng_init()

Moves plat_rng_init() definition from platform source file rng_seed.c
to core driver source stm32_rng.c. There is no platform magic needed
in this funct

drivers: stm32_rng: implement plat_rng_init()

Moves plat_rng_init() definition from platform source file rng_seed.c
to core driver source stm32_rng.c. There is no platform magic needed
in this function. As a result, seed_rng.c source file is removed.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: introduce CFG_STM32MP1_SHARED_RESOURCES

It is now mandatory to enable CFG_STM32MP1_SHARED_RESOURCES to embed
shared_resources.c.

It is forced enabled for STM32MP15x boards and forced

plat-stm32mp1: introduce CFG_STM32MP1_SHARED_RESOURCES

It is now mandatory to enable CFG_STM32MP1_SHARED_RESOURCES to embed
shared_resources.c.

It is forced enabled for STM32MP15x boards and forced disabled for
STM32MP13x boards.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: register to clock framework

Changes stm32mp1 clock driver to register clocks in the clk framework
upon CFG_DRIVERS_CLK=y. CFG_DRIVERS_CLK=y mandates CFG_EMBED_DTB=y
for that platform.

plat-stm32mp1: register to clock framework

Changes stm32mp1 clock driver to register clocks in the clk framework
upon CFG_DRIVERS_CLK=y. CFG_DRIVERS_CLK=y mandates CFG_EMBED_DTB=y
for that platform.

When CFG_DRIVERS_CLK=y, static array stm32mp1_clk[] holds all registered
clock instances, relating to either a clock gate referred in array
stm32mp1_clk_gate[] and an always on clock from array stm32mp1_clk_on[].

Defines local helper functions clock_id_to_gate_index() and
clock_id_to_always_on_index() to convert generic clock references
into a platform local clock identifier that is the index of the target
clock in its relative clock references array.


When CFG_DRIVERS_CLK is disabled, stm32mp1 clock legacy functions
stm32_clock_*() call local clock driver. When CFG_DRIVERS_CLK=y, they
call the generic clock API functions clk_*(). These platform clock legacy
functions are preserved since used in platform specific functions
implementation.

To optimize unpaged memory footprint, only few clock names are
embedded and only upon debug trace level and only required clk_ops
operators are linked in an unpaged memory section.

Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: CFG_STM32MP1_SCMI_SIP=y embeds SCMI SiP SMC entry

Define configuration switch CFG_STM32MP1_SCMI_SIP=y/n to enable
SiP SMC platform entries in SCMI server.

Signed-off-by: Etienne Carr

plat-stm32mp1: CFG_STM32MP1_SCMI_SIP=y embeds SCMI SiP SMC entry

Define configuration switch CFG_STM32MP1_SCMI_SIP=y/n to enable
SiP SMC platform entries in SCMI server.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: check TZC400 configuration

Core checks TZC400 configuration during initialization to ensure
DDR firewall expectations are satisfied.

Signed-off-by: Etienne Carriere <etienne.carriere

plat-stm32mp1: check TZC400 configuration

Core checks TZC400 configuration during initialization to ensure
DDR firewall expectations are satisfied.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: seed PRNG with STM32 RNG

Initialize the core PRNG with samples from the SoC RNG during early
initialization. PRNG is used to generate random samples used early
before all services and obvi

stm32mp1: seed PRNG with STM32 RNG

Initialize the core PRNG with samples from the SoC RNG during early
initialization. PRNG is used to generate random samples used early
before all services and obviously device and peripheral drivers
are initialized. Therefore the platform sequence to seed the PRNG
locally handles RNG clock and reset without relying on clock and
reset device OP-TEE drivers as these are not yet initialized.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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plat-stm32mp1: foundation for SCMI service

Embed a SCMI server in stm32mp1 based on SCMI message drivers.
The platform currently supports only the SCMI Base protocol.

Platform provides 2 Arm SMCCC

plat-stm32mp1: foundation for SCMI service

Embed a SCMI server in stm32mp1 based on SCMI message drivers.
The platform currently supports only the SCMI Base protocol.

Platform provides 2 Arm SMCCC fastcall communication channels each
using a small shared memory buffer is SYSRAM manage with a SMT header
for SCMI message exchange.

Default disable CFG_CORE_ASLR, CFG_LOCKDEP, CFG_TEE_CORE_DEBUG and
CFG_UNWIND for TEE RAM memory constraints since SCMI server with a
fastcall message processing path consumes several pages of SoC internal
SYSRAM where TEE pager resides.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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plat-stm32mp1: prepare for SiP SMC services

Implement secure monitor platform handlers foundations for
platform stm32mp1 to handle SiP SMC services.

Signed-off-by: Etienne Carriere <etienne.carrier

plat-stm32mp1: prepare for SiP SMC services

Implement secure monitor platform handlers foundations for
platform stm32mp1 to handle SiP SMC services.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: shres: registering shared resources

This change implements a driver for the stm32mp1 resources that may
be assigned to either secure or non-secure worlds upon the platform
configuration.

stm32mp1: shres: registering shared resources

This change implements a driver for the stm32mp1 resources that may
be assigned to either secure or non-secure worlds upon the platform
configuration.

Other drivers shall register their resources (when applicable) using
the API functions stm32mp_register_{secure|non_secure}_periph*():
- stm32mp_register_*_periph() registers a resource from its
platform ID.
- stm32mp_register_*_periph_iomem() registers a resource from its
IOMEM base address.
- stm32mp_register_*_periph_gpio() registers a resource from its
GPIO reference, bank and position.

Shared resource driver exports some APIs to query a resource
registration state, stm32mp_periph_is_*(),
stm32mp_gpio_bank_is_*(), stm32mp_clock_is_*().

The driver saves the peripheral assignation. The API does not
allow peripherals to change state at runtime. Moverover, to
prevent testing a resource status before it is registered,
the first query on a resource state locks further registering.
Later attempt to register a peripheral will panic the core.

Resources are either secure on non-secure but clock that maybe
shared in which case it will be assigned to the secure world but
a platform service will allow non-secure to access the resource
(i.e. enable/disable the clock). Note such service is out of the
scope of this change, yet this explains API stm32mp_clock_is_shared().

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: RCC support

RCC if the SoC interface for clocks, reset and some low power features.
The drivers is very specific to the platform stm32mp1 hence located
next to the platform specific source

stm32mp1: RCC support

RCC if the SoC interface for clocks, reset and some low power features.
The drivers is very specific to the platform stm32mp1 hence located
next to the platform specific source files.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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stm32mp1: move PSCI in pm/psci.c

Source file pm/psci.c will soon hold several PSCI functions and sequences.
Move now the existing PSCI_CPU_ON support to pm/psci.c.

Signed-off-by: Etienne Carriere <

stm32mp1: move PSCI in pm/psci.c

Source file pm/psci.c will soon hold several PSCI functions and sequences.
Move now the existing PSCI_CPU_ON support to pm/psci.c.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: add initial support

Introduce platform stm32mp1 with board stm32mp1-stm32mp157c-ev1 based
on stm32mp1 SoC family integrating Arm Cortex-A7 technology. In its
default configuration, st

plat-stm32mp1: add initial support

Introduce platform stm32mp1 with board stm32mp1-stm32mp157c-ev1 based
on stm32mp1 SoC family integrating Arm Cortex-A7 technology. In its
default configuration, stm32mp1 OP-TEE core operates in a 256kB secure
RAM with pager support enabled.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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