| #
7122f387 |
| 14-Dec-2024 |
leisen <leisen1@huawei.com> |
drivers: crypto: hisilicon: add pbkdf2 algorithm
Add pbkdf2 algorithm for hisilicon SEC driver.
Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
c7f9abce |
| 21-Nov-2023 |
Xiaoxu Zeng <zengxiaoxu@huawei.com> |
drivers: implement HiSilicon Queue Management (QM) module
The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management
drivers: implement HiSilicon Queue Management (QM) module
The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management module QM is used to interact with software.
Each accelerator module integrates a QM. Software issues tasks to the SQ
(Submmision Queue),and the QM obtains the address of the SQE (Submmision
Queue Element). The BD (Buffer Description, same as SQE) information is
sent to the accelerator. After the task processing is complete, the
accelerator applies for a write-back address from the QM to write back
the SQ.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| #
fb5592f9 |
| 09-Oct-2023 |
loubaihui <loubaihui1@huawei.com> |
core: drivers: add HiSilicon TRNG implementation
Based on HiSilicon hardware, a matching TRNG module is added.
The driver is enabled for the D06 platform (PLATFORM=d06).
Signed-off-by: loubaihui <l
core: drivers: add HiSilicon TRNG implementation
Based on HiSilicon hardware, a matching TRNG module is added.
The driver is enabled for the D06 platform (PLATFORM=d06).
Signed-off-by: loubaihui <loubaihui1@huawei.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
[jf: amend commit description]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
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| #
de7a768c |
| 30-Nov-2022 |
Xiaoxu Zeng <zengxiaoxu@huawei.com> |
drivers: implement lpc_uart driver
Support for lpc_uart that is a serial driver.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: J
drivers: implement lpc_uart driver
Support for lpc_uart that is a serial driver.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
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| #
d7205770 |
| 31-Oct-2022 |
Xiaoxu Zeng <zengxiaoxu@huawei.com> |
core: Add support for Hisilicon D06 (PLATFORM=d06)
D06 is a server-class development board equipped with a Hisilicon
Phosphor processor.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Acked-by:
core: Add support for Hisilicon D06 (PLATFORM=d06)
D06 is a server-class development board equipped with a Hisilicon
Phosphor processor.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
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