| #
6898b2ca |
| 01-Apr-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: pmull_ghash_update_*() accepts unaligned payload
Updates the relevant ld1 and vld1 instructions for AArch64 and AArch32
respectively to allow unaligned src and head parameters.
Reviewed-
core: arm: pmull_ghash_update_*() accepts unaligned payload
Updates the relevant ld1 and vld1 instructions for AArch64 and AArch32
respectively to allow unaligned src and head parameters.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
a31e8303 |
| 01-Apr-2020 |
Jerome Forissier <jerome@forissier.org> |
Remove '.section .text.<name>' and use function macros instead
Assembler functions are normally defined using the FUNC/LOCAL_FUNC
macros from <asm.S>. The macros takes care of several things, includ
Remove '.section .text.<name>' and use function macros instead
Assembler functions are normally defined using the FUNC/LOCAL_FUNC
macros from <asm.S>. The macros takes care of several things, including
putting the function in a specific section for later garbage collection
by the linker (--gc-sections).
A few files do not follow this convention, let's fix them. Two
functions in ghash-ce-core_a64.S (pmull_gcm_load_round_keys() and
pmull_gcm_aes_sub()) totally lack a .section directive, which I think
is a mistake. Fix them at the same time.
No functional change is expected.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
27e19499 |
| 10-Sep-2019 |
Jerome Forissier <jerome@forissier.org> |
core: ltc: force alignment of A32 assembler functions to 4 bytes
The Clang assembler will not align all the functions containing A32
code (as opposed to thumb) on 4-byte boundaries, contrary to GCC.
core: ltc: force alignment of A32 assembler functions to 4 bytes
The Clang assembler will not align all the functions containing A32
code (as opposed to thumb) on 4-byte boundaries, contrary to GCC.
This can cause a runtime exception (undef-abort).
Add a ".balign 4" to the ENTRY macro to fix that.
See also commit ff7c2da6d14b ("Force alignment of assembler functions
(FUNC and LOCAL_FUNC) to 4 bytes") [1].
Link: [1] https://github.com/OP-TEE/optee_os/commit/ff7c2da6d14b
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
fb7ef469 |
| 15-Dec-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
Reformat copyright/license header in files with an SPDX ID
Some files were committed with an SPDX license identifier before the
rules were defined [1]. Reformat them accordingly.
[1] documentation/
Reformat copyright/license header in files with an SPDX ID
Some files were committed with an SPDX license identifier before the
rules were defined [1]. Reformat them accordingly.
[1] documentation/copyright_and_license_headers.rst
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
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| #
f6e4d9f7 |
| 16-Nov-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: import GHASH acceleration routines
Imports assembly code for accelerated GHASH computations and provides an
interface for using these low level functions.
The assembly code relies on features
core: import GHASH acceleration routines
Imports assembly code for accelerated GHASH computations and provides an
interface for using these low level functions.
The assembly code relies on features now available in all ARM cores. No
assembly code is enabled at all unless CFG_CRYPTO_WITH_CE = y. Code
using the PMULL/PMULL2 instruction is enabled with CFG_HWSUPP_PMULL = y.
The assembly code is written by Ard Biesheuvel
<ard.biesheuvel@linaro.org> and modified slightly here to fit better
into OP-TEE.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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