| c60ed582 | 10-Mar-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm64: SHAKE128 using ARMv8.2-A cryptographic extensions
Adds support for SHAKE128 or SHA3-128 sized blocks in
sha3_ce_transform().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
A
core: arm64: SHAKE128 using ARMv8.2-A cryptographic extensions
Adds support for SHAKE128 or SHA3-128 sized blocks in
sha3_ce_transform().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| bfedef0c | 10-Mar-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm64: SHA-3 using ARMv8.2-A cryptographic extensions
Import SHA-3 assembly code from the Linux kernel (Linaro contribution).
Enabled with CFG_CRYPTO_SHA3_ARM_CE=y, set by default if
CFG_CRYPT
core: arm64: SHA-3 using ARMv8.2-A cryptographic extensions
Import SHA-3 assembly code from the Linux kernel (Linaro contribution).
Enabled with CFG_CRYPTO_SHA3_ARM_CE=y, set by default if
CFG_CRYPTO_WITH_CE82=y.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 2be3770e | 16-Mar-2023 |
Xu Yizhou <xuyizhou1@huawei.com> |
core: arm64: SM4 CE optimization for ARMv8.2
Enabled with CFG_CRYPTO_SM4_ARM_CE=y, set by default if
CFG_CRYPTO_WITH_CE82=y.
Signed-off-by: Xu Yizhou <xuyizhou1@huawei.com>
Acked-by: Tianjia Zhang
core: arm64: SM4 CE optimization for ARMv8.2
Enabled with CFG_CRYPTO_SM4_ARM_CE=y, set by default if
CFG_CRYPTO_WITH_CE82=y.
Signed-off-by: Xu Yizhou <xuyizhou1@huawei.com>
Acked-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 76dd08ed | 30-Mar-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: optimize AArch64 AES-GCM routines
Optimize handling of the last odd AES-GCM block by reusing function
recently added to boost AArch32 performance. Resulting in a small gain
in performance and
core: optimize AArch64 AES-GCM routines
Optimize handling of the last odd AES-GCM block by reusing function
recently added to boost AArch32 performance. Resulting in a small gain
in performance and fewer lines of code.
With this patch together with the recent changes the throughput of
AArch64 AES-GCM has increased from around 400MiB/s to 470MiB/s with
blocks of 4096 bytes.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9cd2e73b | 30-Mar-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: optimize AArch32 AES-GCM routines
In AArch32 there are not enough SIMD registers to make a fused GHASH and
AES-CTR assembly function. But we can do better than using the default
implementation
core: optimize AArch32 AES-GCM routines
In AArch32 there are not enough SIMD registers to make a fused GHASH and
AES-CTR assembly function. But we can do better than using the default
implementation. By carefully using the GHASH and AES primitive assembly
functions there's some gain in performance.
Before this patch throughput was around 12MiB/s to now a bit more than
110MiB/s with blocks of 4096 bytes.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7756183f | 30-Mar-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add ce_aes_xor_block()
Adds ce_aes_xor_block() which xors two memory blocks of size
TEE_AES_BLOCK_SIZE and saves the result back into memory. The operations
are done with SIMD instructions so
core: add ce_aes_xor_block()
Adds ce_aes_xor_block() which xors two memory blocks of size
TEE_AES_BLOCK_SIZE and saves the result back into memory. The operations
are done with SIMD instructions so the memory blocks may be unaligned,
but VFP must be enabled with thread_kernel_enable_vfp().
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 8a15c688 | 30-Mar-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: update AArch64 GHASH acceleration routines
Update AArch64 GHASH acceleration routines for improved performance.
The core parts of assembly and wrapper updates are written by
Ard Biesheuvel <a
core: update AArch64 GHASH acceleration routines
Update AArch64 GHASH acceleration routines for improved performance.
The core parts of assembly and wrapper updates are written by
Ard Biesheuvel <ard.biesheuvel@linaro.org>, see [1].
Link: [1] https://github.com/torvalds/linux/commit/22240df7ac6d76a271197571a7be45addef2ba15
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d7fd8f87 | 30-Mar-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: crypto: unaligned aes-gcm acceleration
The Arm CE code supports working with unaligned data. In order to make
full use of that is the generic __weak function
internal_aes_gcm_update_payload_bl
core: crypto: unaligned aes-gcm acceleration
The Arm CE code supports working with unaligned data. In order to make
full use of that is the generic __weak function
internal_aes_gcm_update_payload_block_aligned() replaced with
internal_aes_gcm_update_payload_blocks(). The latter now supports
working with unaligned buffers.
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 6898b2ca | 01-Apr-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: pmull_ghash_update_*() accepts unaligned payload
Updates the relevant ld1 and vld1 instructions for AArch64 and AArch32
respectively to allow unaligned src and head parameters.
Reviewed-
core: arm: pmull_ghash_update_*() accepts unaligned payload
Updates the relevant ld1 and vld1 instructions for AArch64 and AArch32
respectively to allow unaligned src and head parameters.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 75fea8a9 | 30-Mar-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add accelerated SHA-256 routines
Adds an Arm CE accelerated SHA-256 function to core/arch/arm/crypto. The
code originates from the previous implementation inside LTC library.
With this multipl
core: add accelerated SHA-256 routines
Adds an Arm CE accelerated SHA-256 function to core/arch/arm/crypto. The
code originates from the previous implementation inside LTC library.
With this multiple crypto libraries can share the function.
The old CFG_CRYPTO_SHA256_ARM64_CE and CFG_CRYPTO_SHA256_ARM32_CE are
replaced by CFG_CRYPTO_SHA256_ARM_CE.
CFG_CORE_CRYPTO_SHA256_ACCEL is introduced as to indicate that some kind of
SHA-256 acceleration is available, not necessarily based on Arm CE.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 858d5279 | 30-Mar-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add accelerated SHA1 routines
Adds an Arm CE accelerated SHA1 function to core/arch/arm/crypto. The code
originates from the previous implementation inside LTC library. With
this multiple cryp
core: add accelerated SHA1 routines
Adds an Arm CE accelerated SHA1 function to core/arch/arm/crypto. The code
originates from the previous implementation inside LTC library. With
this multiple crypto libraries can share the function.
The old CFG_CRYPTO_SHA1_ARM64_CE and CFG_CRYPTO_SHA1_ARM32_CE are
replaced by CFG_CRYPTO_SHA1_ARM_CE.
CFG_CORE_CRYPTO_SHA1_ACCEL is introduced as to indicate that some kind of
SHA-1 acceleration is available, not necessarily based on Arm CE.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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